HY57V283220(L)T(P)/ HY5V22(L)F(P)
4 Banks x 1M x 32Bit Synchronous DRAM
Revision History
Revision No.
0.1
History
Defined Preliminary Specification
1) Modified FBGA Ball Configuration Typo.
2) Changed Functional Block Diagram from A10 to A11.3) Changed VDD min from 3.0V to 3.135V.
4) Changed Cap. Value from C11, 3, 5 to 4pf & C12, 3.8 to 4pf.5) Insert tAC2 Value.
6) Insdrt tRAS & CLK Value.Defined IDD Spec.Delited Preliminary.Changed IDD Spec.133MHz Speed Added
Changed FBGA Package Size from 11x13 to 8x13.1) Changed VDD min from 3.135V to 3.0V.2) Changed VIL min from VSSQ-0.3V to -0.3V.Modified of size erra. (Page15)
(Equation : 13.00±10 -> 13.00±0.10)
Remark
0.2
0.30.40.50.60.70.80.9
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assumeany responsibility for use of circuits described. No patent licenses are implied.Rev. 0.9 / July 2004
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HY57V283220(L)T(P)/ HY5V22(L)F(P)
4 Banks x 1M x 32Bit Synchronous DRAM
DESCRIPTION
The Hynix HY57V283220(L)T(P) / HY5V22(L)F(P) is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for thememory applications which require wide data I/O and high bandwidth. HY57V283220(L)T(P) / HY5V22(L)F(P) is orga-nized as 4banks of 1,048,576x32.
HY57V283220(L)T(P) / HY5V22(L)F(P) is offering fully synchronous operation referenced to a positive edge of theclock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internallypipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or writecycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst countsequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminatecommand or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelineddesign is not restricted by a `2N` rule.)
FEATURES
••••••
JEDEC standard 3.3V power supply
All device pins are compatible with LVTTL interface 86TSOP-II, 90Ball FBGA with 0.8mm of pin pitchAll inputs and outputs referenced to positive edge of system clock
Data mask function by DQM0,1,2 and 3
•
Internal four banks operation
•
Burst Read Single Write operationProgrammable CAS Latency ; 2, 3 Clocks•••
Auto refresh and self refresh4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst
ORDERING INFORMATION
Part No.
HY57V283220(L)T(P)-5HY5V22(L)F(P)-5HY57V283220(L)T(P)-55HY5V22(L)F(P)-55HY57V283220(L)T(P)-6HY5V22(L)F(P)-6HY57V283220(L)T(P)-7HY5V22(L)F(P)-7HY57V283220(L)T(P)-HHY5V22(L)F(P)-HHY57V283220(L)T(P)-8HY5V22(L)F(P)-8HY57V283220(L)T(P)-PHY5V22(L)F(P)-PHY57V283220(L)T(P)-SHY5V22(L)F(P)-S
Clock Frequency
200MHz183MHz166MHz143MHz
OrganizationInterfacePackage
4Banks x 1Mbits x32
133MHz125MHz100MHz100MHz
LVTTL
86TSOP-II90Ball FBGA
Note) Hynix supports lead free part for each speed grade with same specification.
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assumeany responsibility for use of circuits described. No patent licenses are implied.Rev. 0.9 / July 2004
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HY57V283220(L)T(P) / HY5V22(L)F(P)
PIN CONFIGURATION ( HY57V283220(L)T(P) Series)
VDDDQ0VDDQDQ1DQ2VSSQDQ3DQ4VDDQDQ5DQ6VSSQDQ7NCVDDDQM0/WE/CAS/RAS/CSA11BA0BA1A10/APA0A1A2DQM2VDDNCDQ16VSSQDQ17DQ18VDDQDQ19DQ20VSSQDQ21DQ22VDDQDQ23VDD868584838281807978777675747372717069686766656463626160595857565554535251504948474645441234567891011121314151617181920212223242526272829303132333435363738394041424386pin TSOP II400mil x 875mil0.5mm pin pitchVSSDQ15VSSQDQ14DQ13VDDQDQ12DQ11VSSQDQ10DQ9VDDQDQ8NCVSSDQM1NCNCCLKCKEA9A8A7A6A5A4A3DQM3VSSNCDQ31VDDQDQ30DQ29VSSQDQ28DQ27VDDQDQ26DQ25VSSQDQ24VSSPIN DESCRIPTIONPINCLKCKECSBA0, BA1A0 ~ A11ClockClock EnableChip SelectBank AddressAddressRow Address Strobe, Column Address Strobe,Write EnableData Input/Output MaskData Input/OutputPower Supply/GroundData Output Power/GroundNo ConnectionPIN NAMEDESCRIPTIONThe system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK.Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refreshEnables or disables all inputs except CLK, CKE and DQMSelects bank to be activated during RAS activitySelects bank to be read/written during CAS activityRow Address : RA0 ~ RA11, Column Address : CA0 ~ CA7Auto-precharge flag : A10RAS, CAS and WE define the operationRefer function truth table for detailsControls output buffers in read mode and masks input data in write modeMultiplexed data input / output pinPower supply for internal circuits and input buffersPower supply for output buffersNo connectionRAS, CAS, WEDQM0~3DQ0 ~ DQ31VDD/VSSVDDQ/VSSQNCRev. 0.9 / July 2004 3
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HY57V283220(L)T(P) / HY5V22(L)F(P)
Ball CONFIGURATION ( HY5V22(L)F(P) Series)
1ADQ2623456789DQ24VSSVDDDQ23DQ21BDQ28VDDQVSSQVDDQVSSQDQ19CVSSQDQ27DQ25DQ22DQ20VDDQDVSSQDQ29DQ30DQ17DQ18VDDQEVDDQDQ31NCNCDQ16VSSQFVSSDQM3A3A2DQM2VDDGA4A5A6A10A0A1HA7A8NCTop ViewNCBA1A11JCLKCKEA9BA0/CS/RASKDQM1NCNC/CAS/WEDQM0LVDDQDQ8VSSVDDDQ7VSSQMVSSQDQ10DQ9DQ6DQ5VDDQNVSSQDQ12DQ14DQ1DQ3VDDQPDQ11VDDQVSSQVDDQVSSQDQ4RDQ13DQ15VSSVDDDQ0DQ2Ball DESCRIPTION
PIN
CLKCKECSBA0, BA1A0 ~ A11
ClockClock EnableChip SelectBank AddressAddress
Row Address Strobe,
Column Address Strobe, Write Enable
Data Input/Output MaskData Input/OutputPower Supply/GroundData Output Power/GroundNo Connection
PIN NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQMSelects bank to be activated during RAS activitySelects bank to be read/written during CAS activityRow Address : RA0 ~ RA11, Column Address : CA0 ~ CA7Auto-precharge flag : A10
RAS, CAS and WE define the operationRefer function truth table for details
Controls output buffers in read mode and masks input data in write modeMultiplexed data input / output pin
Power supply for internal circuits and input buffersPower supply for output buffersNo connection
RAS, CAS, WEDQM0~3DQ0 ~ DQ31VDD/VSSVDDQ/VSSQNC
Rev. 0.9 / July 2004 4
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HY57V283220(L)T(P) / HY5V22(L)F(P)
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 32 I/O Synchronous DRAM
Self Refresh Logic& TimerRefreshCounterCLKCKECSRASCASWEDQM0DQM1DQM2DQM3Row Active1Mx32 Bank 3Row PreDecoder1Mx32 Bank 2X decoderX decoderX decoder1Mx32 Bank 11Mx32 Bank 0DQ0DQ1I/O Buffer & LogicSense AMP & I/O GateState MachineColumnActiveX decoderMemoryCellArrayColumn PreDecoderDQ30DQ31Y decoderBank SelectColumn AddCounterA0A1Address buffersAddressRegisterBurstCounterA11BA0BA1Mode RegisterCAS LatencyData Out ControlPipe Line ControlRev. 0.9 / July 2004 5
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HY57V283220(L)T(P) / HY5V22(L)F(P)
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient TemperatureStorage Temperature
Voltage on Any Pin relative to VSSVoltage on VDD relative to VSSShort Circuit Output CurrentPower Dissipation
Soldering Temperature Þ Time
TATSTGVIN, VOUTVDD, VDDQIOSPDTSOLDER
Symbol
0 ~ 70-55 ~ 125-1.0 ~ 4.6-1.0 ~ 4.6501260 ⋅ 10
Rating
°C°CVVmAW°C ⋅ Sec
Unit
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION (TA=0 to 70°C)
Parameter
Power Supply VoltageInput high voltageInput low voltage
SymbolVDD, VDDQVIHVIL
Min3.02.0- 0.3
Typ.3.33.00
Max3.6VDDQ + 0.3
0.8
UnitVVV
Note11,21,3
Note :
1.All voltages are referenced to VSS = 0V
2.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration with no input clamp diodes3.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration with no input clamp diodes
AC OPERATING CONDITION (TA=0 to 70°C, 3.0V ≤VDD ≤3.6V, VSS=0V - Note1)
Parameter
AC input high / low level voltage
Input timing measurement reference level voltageInput rise / fall time
Output timing measurement reference level
Output load capacitance for access time measurement
SymbolVIH / VILVtriptR / tFVoutrefCL
Value2.4/0.41.411.430
UnitVVnsVpF
1Note
Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF) For details, refer to AC/DC output load circuit
Rev. 0.9 / July 2004 6
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HY57V283220(L)T(P) / HY5V22(L)F(P)
CAPACITANCE ( HY57V283220T Series) (TA=25°C, f=1MHz, VDD=3.3V)
Parameter
Input capacitance
CLK
A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM0~3
Data input / output capacitance
DQ0 ~ DQ31
Pin
SymbolCI1CI2CI/O
Min2.52.54.0
Max4.04.06.5
UnitpFpFpF
OUTPUT LOAD CIRCUITVtt=1.4VVtt=1.4VRT=500 ΩRT=50 ΩOutputOutput30pFZ0 = 50Ω30pFDC Output Load CircuitAC Output Load CircuitDC CHARACTERISTICS I (DC operating conditions unless otherwise noted)
Parameter
Input leakage currentOutput leakage currentOutput high voltageOutput low voltage
SymbolILIILOVOHVOL
Min.-1-12.4-Max11-0.4
UnituAuAVV
Note12IOH = -2mAIOL = +2mA
Note :
1.VIN = 0 to 3.6V, All other pins are not under test = 0V2.DOUT is disabled, VOUT=0 to 3.6V
Rev. 0.9 / July 2004 7
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HY57V283220(L)T(P) / HY5V22(L)F(P)
DC CHARACTERISTICS II (DC operating conditions unless otherwise noted)
Speed
Parameter
Symbol
Test Condition
-5
Burst length=1, One bank active tRC ≥ tRC(min), IOL=0mACKE ≤ VIL(max), tCK = 10nsCKE ≤ VIL(max), tCK = ∞
CKE ≥ VIH(min), CS ≥ VIH(min),
tCK = 10ns Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
-55
-6
-7
-H
-8
-P
S
Unit
Note
Operating CurrentIDD11201201101001001009090mA1
Precharge Standby Current in power down mode
IDD2PIDD2PS
2
mA
1
IDD2N
Precharge Standby Current in non power down mode
IDD2NS
14
mA
9
CKE ≥ VIH(min), tCK = ∞Input signals are stable.CKE ≤ VIL(max), tCK = 10nsCKE ≤ VIL(max), tCK = ∞
CKE ≥ VIH(min), CS ≥ VIH(min),
tCK = 10ns Input signals are changed
IDD3P
Active Standby Current in power down mode
IDD3PS
7
mA
6
IDD3N
Active Standby Current in non power down mode
IDD3NS
one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2VCKE ≥ VIH(min), tCK = ∞Input signals are stable.
ttCK ≥ tCK(min), IOL=0mA
CL=3CL=2
230-170
220-160
200-150
180-140
17
mA
13
Burst Mode Operating Current
180-1402
150-140
130130140
130
mA
130140
mA
23
mA
41
IDD4
All banks active
IDD5
Auto Refresh CurrenttRC ≥ tRC(min), All banks active
Self Refresh CurrentIDD6CKE ≤ 0.2V
0.8
Note :
1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II3.HY57V283220T(P)(HY5V22F(P))-5/55/6/7/H/8/P/S4.HY57V283220LT(P)(HY5V22LF(P))-5/55/6/7/H/8/P/S
Rev. 0.9 / July 2004 8
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HY57V283220(L)T(P) / HY5V22(L)F(P)
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
-5
Parameter
Symbol
Min5
10001022--1.51.511.511.511.511----4.56----------4.56
102.252.25--21.511.511.511.511----56----------56
Max
Min5.5
1000
102.52.5--21.511.511.511.511----5.56----------5.56
Max
Min6
1000
1033--21.7511.7511.7511.7511----5.56----------5.56
Max
Min7
1000
1033--21.7511.7511.7511.7511----5.56----------5.56
Max
Min7.5
1000
-1033--2212121211----66----------66
Max
Min8
1000
1033--2212121211----66----------66
Max
Min10
1000
1233--2212121211----66----------66
Max
Min10
1000
nsnsnsns
2
2tAC2CASLatency=tOHtDStDHtAStAHtCKStCKHtCStCHtOLZtOHZ3
nsnsnsnsnsnsnsnsnsnsnsnsns
31111111111
Max
ns
-55
-6
-7
-H
-8
-P
-S
UnitNote
tCK3CAS Latency = 3System clock cycle time
CASLatency=2tCK2
Clock high pulse width Clock low pulse width Access time from clock
CAS Latency = 3tCLWtAC3tCHW
Data-out hold timeData-Input setup time
Data-Input hold timeAddress setup time
AddressholdtimeCKE setup timeCKEholdtimeCommand setup timeCommandholdtime
CLKtodataoutputinlowZ-time
CAS Latency = 3
CLK to data output
in high Z-time
CASLatency=2tOHZ2
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v
3.Data-out hold time to be measured under 30pF load condition, without Vt termination
Rev. 0.9 / July 2004 9
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HY57V283220(L)T(P) / HY5V22(L)F(P)
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
-5
Parameter
Operation Auto Refresh
tRCtRRCtRCDSymbol
Min555515
Max---100
K-------------64
-55Min555516.5
Max---100K-------------64
Min606018
-6Max---100K-------------64
Min636320
-7Max---100K-------------64
-HMin636320
Max---100K-------------64
Min646420
-8Max---100K-------------64
Min707020
-PMax---100K-------------64
Min707020
-S
Unit
Max---100K-------------64
nsnsns
Note
RAS cycle timeRAS to CAS delay RAS active time RAS precharge time RAS to RASbankactivedelay CAS to CASdelay
Writecommandtodata-indelayData-intoprechargecommandData-intoactivecommandDQMtodata-outHi-ZDQMtodata-inmaskMRStonewcommand
tRAS38.738.7424242485050ns
tRPtRRDtCCDtWTLtDPLtDALtDQZtDQMtMRD
15210142023211-
16.5210142023211-
18210142023211-
20210142023211-
20210142023211-
20210142023211-
202010142023211-
202010142023211-
nsCLKCLKCLKCLKCLKCLKCLKCLKCLKCLKCLKCLKms
1
Precharge to data output Hi-Z
CASLatency=3tPROZ3CASLatency=2tPROZ2
tPDEtSREtREF
PowerdownexittimeSelfrefreshexittimeRefresh Time
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 0.9 / July 2004 10
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HY57V283220(L)T(P) / HY5V22(L)F(P)
DEVICE OPERATING OPTION TABLE
HY5xxxxxxxxx(P)-5
CAS Latency
200MHz(5ns)183MHz(5.5ns)166MHz(6ns)3CLKs3CLKs3CLKstRCD3CLKs3CLKs3CLKstRAS8CLKs8CLKs7CLKstRC11CLKs10CLKs10CLKstRP3CLKs3CLKs3CLKstAC4.5ns5ns5.5nstOH1.5ns2ns2nsHY5xxxxxxxxx(P)-55
CAS Latency
183MHz(5.5ns)166MHz(6ns)143MHz(7ns)3CLKs3CLKs3CLKstRCD3CLKs3CLKs3CLKstRAS7CLKs7CLKs6CLKstRC10CLKs10CLKs9CLKstRP3CLKs3CLKs3CLKstAC5ns5.5ns5.5nstOH2ns2ns2nsHY5xxxxxxxxx(P)-6
CAS Latency
166MHz(6ns)143MHz(7ns)125MHz(8ns)3CLKs3CLKs3CLKstRCD3CLKs3CLKs3CLKstRAS7CLKs6CLKs6CLKstRC10CLKs9CLKs9CLKstRP3CLKs3CLKs3CLKstAC5.5ns5.5ns6nstOH2ns2ns2.5nsHY5xxxxxxxxx(P)-7
CAS Latency
143MHz(7ns)125MHz(8ns)100MHz(10ns)3CLKs3CLKs2CLKstRCD3CLKs3CLKs2CLKstRAS6CLKs6CLKs5CLKstRC9CLKs9CLKs7CLKstRP3CLKs3CLKs2CLKstAC5.5ns6ns6nstOH2ns2ns2nsHY5xxxxxxxxx(P)-H
CAS Latency
133MHz(7.5ns)125MHz(8ns)100MHz(10ns)3CLKs3CLKs2CLKstRCD3CLKs3CLKs2CLKstRAS6CLKs6CLKs5CLKstRC9CLKs9CLKs7CLKstRP3CLKs3CLKs2CLKstAC5.5ns6ns6nstOH2ns2ns2nsHY5xxxxxxxxx(P)-8
CAS Latency125MHz(8ns)100MHz(10ns)83MHz(12ns)
tRCD
tRAS
tRC
tRP
tAC
tOH
3CLKs2CLKs2CLKs
3CLKs2CLKs2CLKs
6CLKs5CLKs4CLKs
9CLKs7CLKs6CLKs
3CLKs2CLKs2CLKs
6ns6ns6ns
2ns2ns2.5ns
Rev. 0.9 / July 2004 11
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HY57V283220(L)T(P) / HY5V22(L)F(P)
HY5xxxxxxxxx(P)-P
CAS Latency100MHz(10ns)83MHz(12ns)66MHz(15ns)2CLKs2CLKs2CLKstRCD2CLKs2CLKs2CLKstRAS5CLKs5CLKs4CLKstRC7CLKs7CLKs6CLKstRP2CLKs2CLKs2CLKstAC6ns6ns6nstOH2ns2.5ns2.5nsHY5xxxxxxxxx(P)-S
CAS Latency100MHz(10ns)83MHz(12ns)66MHz(15ns)3CLKs2CLKs2CLKstRCD2CLKs2CLKs2CLKstRAS5CLKs5CLKs4CLKstRC7CLKs7CLKs6CLKstRP2CLKs2CLKs2CLKstAC6ns6ns6nstOH2ns2.5ns2.5nsRev. 0.9 / July 2004 12
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HY57V283220(L)T(P) / HY5V22(L)F(P)
COMMAND TRUTH TABLE
Command
Mode Register SetNo OperationBank ActiveRead
Read with AutoprechargeWrite
Write with AutoprechargePrecharge All BanksPrecharge selected BankBurst StopDQMAuto Refresh
Burst-Read-Single-WRITE
Entry
Self Refresh1
Exit
CKEn-1
HHHH
CKEnXXXX
CSLHLLL
RASLXHLH
CASLXHHL
WELXHHH
DQMXXXX
CA
RA
LHLHHLXXX
A9 Pin High
(Other Pins OP code)
3
ADDR
A10/APOP code
X
BANote
VV
HXLHLLXCAVXV
HHHHHHL
XX
LL
LHX
HH
LL
XXV
X
HXLH
LLLHLHLHLHL
LLLXHXHXHXV
X
LLLXHXHXHXV
HLHXHXHXHXV
XXXX
X
Entry
Precharge power down
Exit
HLX
X
X
LH
Clock Suspend
EntryExit
HL
LH
XX
X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don¢t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation
3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1.
Rev. 0.9 / July 2004 13
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HY57V283220(L)T(P) / HY5V22(L)F(P)
PACKAGE INFORMATION (HY57V283220T(P) Series)400mil 86pin Thin Small Outline PackageUnit : mm(inch)22.327(0.8790)22.149(0.8720)11.938(0.4700)11.735(0.4620)10.262(0.4040)10.058(0.3960)0.150(0.0059)0.050(0.0020)1.194(0.0470)0.991(0.0390)0.50(0.0197)0.21(0.008)0.18(0.007)5deg0deg0.597(0.0235)0.406(0.0160)0.210(0.0083)0.120(0.0047)Rev. 0.9 / July 2004 14
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HY57V283220(L)T(P) / HY5V22(L)F(P)
PACKAGE INFORMATION (HY5V22F(P) Series)90Ball FBGA with 0.8mm of pin pitch(Ball-side view)
6.40
0.80(typ)
pin#1
ID
11.20
0.80 typ
13.00±0.10
5.60±0.5
6.50±0.5
3.20±0.5
8.00
4.00±0.5
Ball Size 0.45±0.05mm
1.20max0.850+/-0.075seating planeRev. 0.9 / July 2004 15
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