af-phy-0143.000

(Level 3)

AF-PHY-0143.000March 2000

af-phy-0143.000Frame Based ATM Interface (Level 3)March 2000

© 2000 by The ATM Forum. This specification/document may be reproduced and distributed in whole, but (exceptas provided in the next sentence) not in part, for internal and informational use only and not for commercial

distribution. Notwithstanding the foregoing sentence, any protocol implementation conformance statements (PICS)or implementation conformance statements (ICS) contained in this specification/document may be separately

reproduced and distributed provided that it is reproduced and distributed in whole, but not in part, for uses other thancommercial distribution. All other rights reserved. Except as expressly stated in this notice, no part of this

specification/document may be reproduced or transmitted in any form or by any means, or stored in any informationstorage and retrieval system, without the prior written permission of The ATM Forum.

The information in this publication is believed to be accurate as of its publication date. Such information is subjectto change without notice and The ATM Forum is not responsible for any errors. The ATM Forum does not assumeany responsibility to update or correct any information in this publication. Notwithstanding anything to the contrary,neither The ATM Forum nor the publisher make any representation or warranty, expressed or implied, concerningthe completeness, accuracy, or applicability of any information contained in this publication. No liability of any kindshall be assumed by The ATM Forum or the publisher as a result of reliance upon any information contained in thispublication.

The receipt or any use of this document or its contents does not in any way create by implication or otherwise:•

Any express or implied license or right to or under any ATM Forum member company's patent, copyright,trademark or trade secret rights which are or may be associated with the ideas, techniques, concepts orexpressions contained herein; nor

Any warranty or representation that any ATM Forum member companies will announce any product(s) and/orservice(s) related thereto, or if such announcements are made, that such announced product(s) and/or service(s)embody any or all of the ideas, technologies, or concepts contained herein; nor

Any form of relationship between any ATM Forum member companies and the recipient or user of thisdocument.

•

•

Implementation or use of specific ATM standards or recommendations and ATM Forum specifications will bevoluntary, and no company shall agree or be obliged to implement them by virtue of participation in The ATMForum.

The ATM Forum is a non-profit international organization accelerating industry cooperation on ATM technology.The ATM Forum does not, expressly or otherwise, endorse or promote any specific products or services.

NOTE: The user's attention is called to the possibility that implementation of the ATM interoperability specificationcontained herein may require use of an invention covered by patent rights held by ATM Forum Member companiesor others. By publication of this ATM interoperability specification, no position is taken by The ATM Forum withrespect to validity of any patent claims or of any patent rights related thereto or the ability to obtain the license to usesuch rights. ATM Forum Member companies agree to grant licenses under the relevant patents they own on

reasonable and nondiscriminatory terms and conditions to applicants desiring to obtain such a license. For additionalinformation contact:

The ATM Forum

Worldwide Headquarters

2570 West El Camino Real, Suite 304Mountain View, CA 94040-1313Tel:+1-650-949-6700Fax:+1-650-949-6705

Page 2 of 30ATM Technical Committee

af-phy-0143.000March 2000

Contact:

PHY Working Group ChairJohn Mick, IDTPhone: xxxxFax: xxxx

E-mail: mick@idt.com

Page 3 of 30Frame Based ATM Interface (Level 3)

EditorChen Goldenberg, Novanet SemiconductorPhone: +972-9-7464411Fax: +972-9-7464422

E-mail: chen@novanetsemi.com

ATM Technical Committee

af-phy-0143.000March 20001234

Frame Based ATM Interface (Level 3)

INTRODUCTION...................................................................................................................................5INTERFACE REFERENCE DEFINITION.........................................................................................6COMPATIBILITY OPTIONS...............................................................................................................7SPECIFICATION SUMMARY.............................................................................................................8

4.1SIGNAL NAMING CONVENTIONS.........................................................................................................84.2BUS WIDTHS......................................................................................................................................84.3CLOCK RATES....................................................................................................................................84.4PACKET INTERFACE SYNCHRONIZATION............................................................................................84.5 PHY AND LINK LAYER INTERFACE EXAMPLE..................................................................................9566.16.26.377.17.27.3

INTERFACE DATA STRUCTURES.................................................................................................12TRANSMIT PACKET INTERFACE DESCRIPTION.....................................................................14

TRANSMIT SIGNALS..........................................................................................................................14EXAMPLES.......................................................................................................................................18AC TIMING......................................................................................................................................20RECEIVE PACKET INTERFACE DESCRIPTION........................................................................22

RECEIVE SIGNALS............................................................................................................................22EXAMPLES.......................................................................................................................................26AC TIMING......................................................................................................................................29

Page 4 of 30ATM Technical Committee

af-phy-0143.000March 2000

Frame Based ATM Interface (Level 3)

1Introduction

This document specifies the ATM Forum’s recommended interface for the interconnection of PhysicalLayer (PHY) devices to ATM/Link Layer devices implementing Frame-Based ATM. The specificationis based on the Saturn Group’s \"POS-PHY Level 3\" interface.

POS-PHY Level 3 was developed to cover all application bit rates up to and including 2.488 Gbit/s. Itdefines the requirements for interoperable single-PHY (one PHY layer device connected to one LinkLayer device) and multi-PHY (multiple PHY layer devices connected to one Link Layer device)

applications. It stresses simplicity of operation to allow forward migration to more elaborate PHY andLink Layer devices.

This specification defines both the physical implementation of the bus and the signaling protocol usedto communicate data and the data structure used to store the data into holding FIFO’s.

Page 5 of 30ATM Technical Committee

af-phy-0143.000March 2000

Frame Based ATM Interface (Level 3)

2Interface Reference Definition

The interface defines the connection between SONET/SDH Physical layer devices and ATM/LinkLayer devices, which can be used to implement several packet-based protocols like HDLC and PPP.

Figure 2.1: FBATM Reference Points

Facility InterfacePHY-Link InterfacePMDDeviceATM/LinkLayerPHYDiagram Definitions

Facility:

ATM/Link Layer:PHY:PHY-LINK:PMD:

An optical fiber transmission facility.Switching Function Layer.

Physical Layer for Packet over SONET.

Physical Layer to ATM/Link Layer electrical interface.Physical Medium Dependent Layer.

The interface specifies the PHY-LINK interface. The Facility Interface (such as SONET OC-48) isdefined by several National and International standards organizations including Bellcore and ITU.

Page 6 of 30ATM Technical Committee

af-phy-0143.000March 2000

Frame Based ATM Interface (Level 3)

3Compatibility Options

This specification does not attempt to be compatible to any existing standard. There is no existingequivalent standard. Specifically, it does not intend to be compatible with UTOPIA. Although this

information is not critical to any implementation, the following bullets highlight the differences betweenthe Utopia and POS-PHY-3 interfaces.

• Allowance for an 8-bit bus or a 32-bit bus interface running at a maximum speed of 104 MHz.

The bus interface is point-to-point (one output driving only one input load).• • • • • •

Byte or double-word (4 bytes) data format that can accommodate variable size packets.Modification to the RSOC/TSOC start of cell signals to identify the start of packets beingtransferred over the interface. Renamed the signals to RSOP/TSOP.

Addition of the REOP/TEOP end of packet signals which delineate the end of packets beingtransferred over the interface.

Addition of the RMOD[1:0]/TMOD[1:0] modulo signals which indicate if the last double-word of thepacket transfer contains 1, 2, 3 or 4 valid bytes of data.

Addition of the RERR/TERR error signals which, during the end of the packet, indicates if thetransferred packet must be discarded/aborted.

Deletion of the RCA signal. Receive interface of the PHY pushes packet data to the Layer device.Multi-port PHY devices are responsible for performing round-robin servicing of their ports. PHYaddress is inserted in-band with the packet data.

Transmit interface of the PHY is selected using an in-band address that is provided on the samebus transferring the packet data.

Addition of the RSX/TSX start of transfer signals which identify when the in-band port address ofthe PHY is on the RDAT/TDAT bus.

Modification of the TCA cell available signals to form the TPA packet available signals. TPA logicvalues are defined based on the FIFO fill level (in terms of bytes). In multi-port PHY devices, PHYstatus indication can be provided using either a polling or a direct status indication scheme.Polled PHY address is provided by a separate address bus and has pipelined timing.

• • •

• Interface FIFO fill level granularity is byte-based. For the Transmit Interface FIFO, the packet

available status and start of transmission FIFO fill levels are programmable. For the ReceiveInterface, the maximum burst transfer size is programmable.

Page 7 of 30ATM Technical Committee

af-phy-0143.000March 2000

Frame Based ATM Interface (Level 3)

44.1

Specification SummarySignal Naming Conventions

The interface where data flows from the ATM/Link Layer device to the Physical layer device will belabeled the Transmit Interface. The interface where data flows from the Physical Layer device to theATM/Link Layer device will be labeled the Receive Interface. All signals are active high unlessdenoted by a trailing \"B\".

SIGNALSIGNALB

Active high signaling.Active low signaling.

4.2Bus Widths

The interface supports an 8-bit and/or a 32-bit data bus structure. The bus interface is point-to-point(one output driving only one input load) and thus a 32-bit data bus would support only one device. Tosupport multiple lower rate devices with point-to-point connections, an 8-bit data bus structure isdefined. Thus, each PHY device would use an 8-bit interface reducing the total number of pinsrequired.

To support variable length packets, the RMOD[1:0]/TMOD[1:0] signals are defined to specify validbytes in the 32-bit data bus structure. Each double-word must contain four valid bytes of packet datauntil the last double-word of the packet transfer which is marked with the end of packet REOP/TEOPsignal. This last double-word of the transfer will contain up to four valid bytes specified by theRMOD[1:0]/TMOD[1:0] signals.

4.3Clock Rates

The interface can support a transfer clock rate up to 104 MHz. Some devices may support multiplerates. Generally, devices targeted at single or multi-PHY applications, where the aggregate PHY bitrate approaches 622 Mbit/s will use the 8-bit data bus structure with a 104 MHz FIFO clock rate.

Devices targeted at applications where the aggregate PHY bit rate approaches 2.4 Gbit/s will use the32-bit data bus structure with a 104 MHz FIFO clock rate.

4.4Packet Interface Synchronization

The packet interface supports transmit and receive data transfers at clock rates independent of theline bit rate. As a result, PHY layer devices must support packet rate decoupling using FIFOs.To ease the interface between the ATM/Link Layer and PHY layer devices and to support multiplePHY layer interfaces, FIFOs are used. Control signals are provided to both the Link Layer and PHYlayer devices to allow either one to exercise flow control. Since the bus interface is point-to-point, thereceive interface of the PHY device pushes data to the Link Layer device. For the transmit interface,the packet available status granularity is byte-based.

In the receive direction, when the PHY layer device has stored an end-of-packet (a complete smallpacket or the end of a larger packet) or some predefined number of bytes in its receive FIFO, it sendsthe in-band address followed by FIFO data to the Link Layer device. The data on the interface bus ismarked with the valid signal (RVAL) asserted. A multi-port PHY device with multiple FIFOs would

Page 8 of 30ATM Technical Committee

af-phy-0143.000Frame Based ATM Interface (Level 3)March 2000

service each port in a round-robin fashion when sufficient data is available in its FIFO. The Link Layerdevice can pause the data flow by deasserting the enable signal (RENB).

In the transmit direction, when the PHY layer device has space for some predefined number of bytesin its transmit FIFO, it informs the Link Layer device by asserting a transmit packet available (TPA).The Link Layer device can then write the in-band address followed by packet data to the PHY layerdevice using an enable signal (TENB). The Link Layer device shall monitor TPA for a high to low

transition, which would indicate that the transmit FIFO is near full (the number of bytes left in the FIFOcan be user selectable, but must be predefined), and suspend data transfer to avoid an overflow. TheLink Layer device can pause the data flow by deasserting the enable signal (TENB).

This interface defines both byte-level and packet-level transfer control in the transmit direction. Inbyte-level transfer, FIFO status information is presented on a cycle-by-cycle basis. With packet-leveltransfer, the FIFO status information applies to segments of data. When using byte level transfer,direct status indication must be used. In this case, the PHY layer device provides the transmit packetavailable status of the selected port (STPA) in the PHY device. As well, the PHY layer device mayprovide direct access to the transmit packet available status of all ports (DTPA[]) in the PHY device ifthe number of ports is small. With packet level transfer, the Link Layer device is able to do statuspolling on the transmit direction. The Link Layer device can use the transmit port address TADR[] topoll individual ports of the PHY device, which all respond on a common polled (PTPA) signal.

Since the variable size nature of packets does not allow any guarantee as to the number of bytes

available, in both transmit and receive directions, a selected PHY transmit packet available is providedon signal STPA and a receive data valid on signal RVAL. STPA and RVAL always reflect the status ofthe selected PHY to or from which data is being transferred. RVAL indicates if valid data is availableon the receive data bus and is defined such that data transfers can be aligned with packet boundaries.Physical layer port selection is performed using in-band addressing. In the transmit direction, theLayer device selects a PHY port by sending the address on the TDAT[] bus marked with the TSXsignal active and TENB signal inactive. All subsequent TDAT[] bus operations marked with the TSXsignal inactive and the TENB active will be packet data for the specified port. In the receive direction,the PHY device will specify the selected port by sending the address on the RDAT[] bus marked withthe RSX signal active and RVAL signal inactive. All subsequent RDAT[] bus operations marked withRSX inactive and RVAL active will be packet data from the specified port.

Both byte-level and packet-level modes are specified in this standard in order to support the currentlow density multi-port physical layer devices and future higher density multi-port devices. When thenumber of ports in the physical layer device is limited, byte-level transfer using DTPA[] signalsprovides a simpler implementation and reduces the need for addressing pins. In this case, directaccess will start to become unreasonable as the number of ports increase. Packet-level transferprovides a lower pin count solution using the TADR[] bus when the number of ports is large. In-bandaddressing ensures the protocol remains consistent between the two approaches. However, the finalchoice left to the system designers and physical layer device manufacturers to select which approachbest suits their desired applications.

4.5 PHY and Link Layer Interface Example

Figure 4.1 illustrates a conceptual example of how a single multi-port PHY device may be interfaced toa Link Layer device. In the example, the Link Layer device is connected to a single package fourchannel PHY layer device using the 32-bit interface. Figure 4.2 illustrates a conceptual example ofhow multi-port PHY devices may be interfaced to a single Link Layer device. The Link Layer device isconnected to two four-channel PHY layer devices using 8-bit interfaces.

In both examples, the PHY devices are using the direct status indication signals DTPA[]. Optionally,the Link Layer device can perform multiplexed status polling using the PTPA signals.

Page 9 of 30ATM Technical Committee

af-phy-0143.000Frame Based ATM Interface (Level 3)

March 2000

Figure 4.1: FB-ATM PHY to Link Layer 32-bit Interface

POS-PHY BusLink Layer DeviceMulti-Port PHYDeviceTFCLKTFCLKTENBTENBTDAT[31:0]TDAT[31:0]OpticalTMOD[1:0]TMOD[1:0]TransceiverTPRTYTPRTYTSOPTSOPTEOPTEOPTERRTERRTSXTSXOpticalTransceiverDTPA[3:0]DTPA[3:0]STPASTPAPTPAPTPATADR[1:0]TADR[1:0]OpticalRFCLKRFCLKTransceiverRENBRENBRDAT[31:0]RDAT[31:0]RMOD[1:0]RMOD[1:0]RPRTYRPRTYRVALRVALRSOPRSOPREOPREOPOpticalRERRRERRTransceiverRSXRSXPage 10 of 30ATM Technical Committee

af-phy-0143.000Frame Based ATM Interface (Level 3)

March 2000

Figure 4.2: FB-ATM PHY to Link Layer 8-Bit Interface

POS-PHY BusLink Layer DevicePHY Device #1OpticalTFCLKTFCLKTransceiverTENB[0]TENBTDAT[7:0][0]TDAT[7:0]TPRTY[0]TPRTYTSOP[0]TSOPTEOP[0]TEOPTERR[0]TERROpticalTSX[0]TSXTransceiverDTPA[3:0][0]DTPA[3:0]STPA[0]STPAPTPA[0]PTPATADR[1:0][0]TADR[1:0]OpticalRFCLKRFCLKTransceiverRENB[0]RENBRDAT[7:0][0]RDAT[7:0]RPRTY[0]RPRTYRVAL[0]RVALRSOP[0]RSOPREOP[0]REOPOpticalRERR[0]RERRTransceiverRSX[0]RSXPHY Device #2OpticalTFCLKTFCLKTransceiverTENB[1]TENBTDAT[7:0][1]TDAT[7:0]TPRTY[1]TPRTYTSOP[1]TSOPTEOP[1]TEOPTERR[1]TERROpticalTSX[1]TSXTransceiverDTPA[3:0][1]DTPA[3:0]STPA[1]STPAPTPA[1]PTPATADR[1:0][1]TADR[1:0]OpticalRFCLKRFCLKTransceiverRENB[1]RENBRDAT[7:0][1]RDAT[7:0]RPRTY[1]RPRTYRVAL[1]RVALRSOP[1]RSOPREOP[1]REOPOpticalRERR[1]RERRTransceiverPage 11 of 30ATM Technical Committee

af-phy-0143.000March 2000

Frame Based ATM Interface (Level 3)

5Interface Data Structures

Packets shall be written into the transmit FIFO and read from the receive FIFO using a defined datastructure. Octets are written in the same order they are to be transmitted or they were received on theSONET line. Within an octet, the MSB (bit 7) is the first bit to be transmitted. The interfacespecification does not preclude the transfer of 1-byte packets. In this case, both start of packet andend of packet signals shall be asserted simultaneously.

For packets longer than the PHY device FIFO, the packet must be transferred over the bus interfacein sections. The number of bytes of packet data in each section may be fixed or variable dependingon the application. In general, the Receive Interface will round-robin between receive FIFOs with filllevels exceeding a programmable high water mark or with at least one end of packet stored in theFIFO. The Receive Interface would end the transfer of data when an end of a packet is transferred orwhen a programmable number of bytes have been transferred. The Link Layer device may send fixedsize sections of packets on the Transmit Interface or use the TPA signal to determine when the FIFOreaches a full level.

Figure 5.1 illustrates the data structure for the 32-bit bus interface. The double-word with the last byteof the packet is marked with TEOP asserted and TMOD[1:0] specifying the number of valid bytes.Figure 5.2 illustrates the data structure for the 8-bit bus interface. The first byte of the packet ismarked with TSOP asserted. The last byte of the packet is marked with TEOP asserted. In all cases,the PHY address is marked with TSX asserted.

In both illustrations, the in-band port address for multi-port PHY devices is not shown. The TransmitInterface would send the PHY port address, on the same bus as the data, marked with the TSX signalactive and the TENB signal inactive. Subsequent data transfers on the Transmit Interface would usethe transmit FIFO selected by the in-band address. On the Receive Interface, the PHY device reportsthe receive FIFO address in-band with the RSX signal active and the RVAL signal inactive beforetransferring packet data. For both cases, large packets which exceed the FIFO size will betransferred over the interface in sections with appropriate in-band addressing prefixing each section.The in-band address is specified in a single clock cycle operation marked with the RSX/TSX signals.The port address is specified by the TDAT[7:0]/RDAT[7:0] signals. The address is the numeric valueof the TDAT[7:0]/RDAT[7:0] signals where bit 0 is the least significant bit and bit 7 is the mostsignificant bit. Thus, up to 256 ports may be supported by a single interface. With a 32-bit interface,the upper 24 bits shall be ignored.

The specification does not define the usage of any packet data. In particular, it does not define anyfield for error correction. Notice that if the Link Layer device uses the PPP protocol, a Frame CheckSequence (FCS) must be processed. If the Physical Layer device does not insert the FCS field beforetransmission, these bytes should be included at the end of the packet. If the Physical Layer devicedoes not strip the FCS field in the receive direction, these bytes will be included at the end of thepacket.

Page 12 of 30ATM Technical Committee

af-phy-0143.000March 2000

Frame Based ATM Interface (Level 3)

Figure 5.1: 32-bit Interface Data Structures

Bit 31Bit 24Bit 23Bit 16Bit 15Bit 8Bit 7Bit 0Dword 1Dword 2Dword 3Dword 4Dword 5Dword 6Byte 1Byte 5Byte 9Byte 13Byte 17Byte 21Byte 2Byte 6Byte 10Byte 14Byte 18Byte 22Byte 3Byte 7Byte 11Byte 15Byte 19Byte 23Byte 4Byte 8Byte 12Byte 16Byte 20Byte 24Dword 28Byte 109XXXXXXA 109 Byte PacketFigure 5.2: 8-bit Interface Data Structures

Bit 7Bit 0Byte 1Byte 2Byte 3Byte 4Byte 5Byte 6Byte 1Byte 2Byte 3Byte 4Byte 5Byte 6Byte 62Byte 62A 62 Byte PackePage 13 of 30ATM Technical Committee

af-phy-0143.000March 2000

Frame Based ATM Interface (Level 3)

6Transmit Packet Interface Description

The standard FIFO depth for the interface is 256 octets. The transmit buffer shall have aprogrammable threshold defined in terms of the number of bytes available in the FIFO for theassertion and deassertion of the transmit packet available flags.

In this fashion, transmit latency can be managed, and advance TPA lookahead can be achieved. Thiswill allow a Link Layer device to continue to burst data in, without overflowing the transmit buffer, afterTPA has been deasserted.

In the transmit direction, the PHY layer device shall not initiate data transmission before a predefinednumber of bytes or an end of packet flag has been stored in the transmit FIFO. This capability doesnot affect the bus protocol, but is required to avoid transmit FIFO underflow and frequent dataretransmission by the higher layers.

6.1Transmit Signals

Table 6.1 lists the transmit side signals. All signals are expected to be updated and sampled usingthe rising edge of the transmit FIFO clock TFCLK. A fully compatible POS-PHY Physical Layer devicerequires at least a 256 byte deep FIFO.

Table 6.1: Transmit Signal Descriptions

Signal Name

TFCLK

Direction

Clock Source toLink and PHY

Function

Transmit FIFO Write Clock (TFCLK).

TFCLK is used to synchronize data transfer transactionsbetween the LINK Layer device and the PHY layer device.TFCLK may cycle at a rate up to 104 MHz.Transmit Error Indicator (TERR) signal.

TERR is used to indicate that there is an error in the currentpacket. When TERR is set high, the current packet is aborted.TERR should only be asserted when TEOP is asserted; it isconsidered valid only when TENB is simultaneously asserted.

TERRLINK to PHY

TENBLINK to PHY

Transmit Write Enable (TENB) signal.

The TENB signal is used to control the flow of data to the

transmit FIFOs. When TENB is high, the TDAT, TMOD, TSOP,TEOP and TERR signals are invalid and are ignored by the PHY.The TSX signal is valid and is processed by the PHY whenTENB is high.

When TENB is low, the TDAT, TMOD, TSOP, TEOP and TERRsignals are valid and are processed by the PHY. Also, the TSXsignal is ignored by the PHY when TENB is low.

Page 14 of 30ATM Technical Committee

af-phy-0143.000March 2000

Frame Based ATM Interface (Level 3)

Signal Name

TDAT[31:0]

Direction

LINK to PHY

Function

Transmit Packet Data Bus (TDAT[]) bus.

This bus carries the packet octets that are written to the selectedtransmit FIFO and the in-band port address to select the desiredtransmit FIFO. The TDAT bus is considered valid only whenTENB is simultaneously asserted.

When a 32-bit interface is used, data must be transmitted in bigendian order on TDAT[31:0]. Given the define data structure, bit31 is transmitted first and bit 0 is transmitted last.When an 8-bit interface is used, the PHY supports onlyTDAT[7:0].

TPRTYLINK to PHY

Transmit bus parity (TPRTY) signal.

The transmit parity (TPRTY) signal indicates the parity calculatedover the TDAT bus. When an 8-bit interface is used, the PHYonly supports TPRTY calculated over TDAT[7:0]. TPRTY isconsidered valid only when TENB or TSX is asserted.

When TPRTY is supported, the PHY layer device is required tosupport odd parity. The PHY layer device is required to reportany parity error to higher layers, but shall not interfere with thetransferred data.

TMOD[1:0]LINK to PHY

Transmit Word Modulo (TMOD[1:0]) signal.

TMOD[1:0] indicates the number of valid bytes of data in

TDAT[31:0]. The TMOD bus should always be all zero, exceptduring the last double-word transfer of a packet on TDAT[31:0].When TEOP is asserted, the number of valid packet data byteson TDAT[31:0] is specified by TMOD[1:0].

TMOD[1:0] = “00”TMOD[1:0] = “01”TMOD[1:0] = “10”TMOD[1:0] = “11”

TDAT[31:0] validTDAT[31:8] validTDAT[31:16] validTDAT[31:24] valid

When an 8-bit interface is used, the TMOD[1:0] bus is notrequired.

TMOD is considered valid only when TENB is simultaneouslyasserted.

TSX

LINK to PHY

Transmit Start of Transfer (TSX) signal.

TSX indicates when the in-band port address is present on theTDAT bus. When TSX is high and TENB is high, the value ofTDAT[7:0] is the address of the transmit FIFO to be selected.Subsequent data transfers on the TDAT bus will fill the FIFOspecified by this in-band address.

For single port PHY devices, the TSX signal is optional as thePHY device will ignore in-band addresses when TENB is high.TSX is considered valid only when TENB is not asserted.

Page 15 of 30ATM Technical Committee

af-phy-0143.000March 2000

Frame Based ATM Interface (Level 3)

Signal Name

TSOP

Direction

LINK to PHY

Function

Transmit Start of Packet (TSOP) signal.

TSOP is used to delineate the packet boundaries on the TDATbus. When TSOP is high, the start of the packet is present onthe TDAT bus.

TSOP is required to be present at the beginning of every packetand is considered valid only when TENB is asserted.

TEOPLINK to PHY

Transmit End of Packet (TEOP) signal.

TEOP is used to delineate the packet boundaries on the TDATbus. When TEOP is high, the end of the packet is present onthe TDAT bus.

When a 32-bit interface is used, TMOD[1:0] indicates the

number of valid bytes the last double-word is composed of whenTEOP is asserted. When an 8-bit interface is used, the last byteof the packet is on TDAT[7:0] when TEOP is asserted.

TEOP is required to be present at the end of every packet and isconsidered valid only when TENB is asserted.

TADR[]LINK to PHYPacket-Level

Mode

Transmit PHY Address (TADR[]) bus.

The TADR bus is used with the PTPA signal to poll the transmitFIFO’s packet available status.

When TADR is sampled on the rising edge of TFCLK by thePHY, the polled packet available indication PTPA signal isupdated with the status of the port specified by the TADRaddress on the following rising edge of TFCLK.

DTPA[]PHY to LINKByte-LevelMode

Direct Transmit Packet Available (DTPA[]).

The DTPA bus provides direct status indication for thecorresponding ports in the PHY device.

DTPA transitions high when a predefined (normally userprogrammable) minimum number of bytes is available in itstransmit FIFO. Once high, the DTPA signal indicates that itscorresponding transmit FIFO is not full. When DTPA transitionslow, it optionally indicates that its transmit FIFO is full or near full(normally user programmable).

DTPA is required if byte-level transfer mode is supported. DTPAis updated on the rising edge of TFCLK.

Page 16 of 30ATM Technical Committee

af-phy-0143.000March 2000

Frame Based ATM Interface (Level 3)

Signal Name

STPA

Direction

PHY to LINKByte-LevelMode

Function

Selected-PHY Transmit Packet Available (STPA) signal.STPA transitions high when a predefined (normally user

programmable) minimum number of bytes are available in thetransmit FIFO specified by the in-band address on TDAT. Oncehigh, STPA indicates the transmit FIFO is not full. When STPAtransitions low, it indicates that the transmit FIFO is full or nearfull (normally user programmable).

STPA always provides status indication for the selected port ofthe PHY device in order to avoid FIFO overflows while polling isperformed. The port which STPA reports is updated on thefollowing rising edge of TFCLK after the PHY address on TDATis sampled by the PHY device.

STPA is required if byte-level transfer mode is supported. STPAis updated on the rising edge of TFCLK.

PTPAPHY to LINKPacket-Level

Mode

Polled-PHY Transmit Packet Available (PTPA) signal.PTPA transitions high when a predefined (normally user

programmable) minimum number of bytes are available in thepolled transmit FIFO. Once high, PTPA indicates that thetransmit FIFO is not full. When PTPA transitions low, itoptionally indicates that the transmit FIFO is full or near full(normally user programmable).

PTPA allows the polling of the PHY selected by the TADRaddress bus. The port which PTPA reports is updated on thefollowing rising edge of TFCLK after the PHY address on TADRis sampled by the PHY device.

PTPA is required if packet-level transfer mode is supported.PTPA is updated on the rising edge of TFCLK.

Page 17 of 30ATM Technical Committee

af-phy-0143.000March 2000

Frame Based ATM Interface (Level 3)

6.2Examples

The following examples are not part of the requirements definition of the compatibility specification.They are only informative and provide an aid in the visualization of the interface operation. Theexamples only present a limited set of scenarios; they are not intended to imply restrictions beyondthat presented in the text of the specification. If any apparent discrepancies exist between theexamples and the text, the text shall take precedence.

The transmit interface is controlled by the Link Layer device using the TENB signal. All signals mustbe updated and sampled using the rising edge of the transmit FIFO clock, TFCLK. Figure 6.1 is anexample of a multi-port PHY device with two channels. The PHY layer device indicates that a FIFO isnot full by asserting the appropriate transmit packet available signal DTPA. DTPA remains asserteduntil the transmit FIFO is almost full. Almost full implies that the PHY layer device can accept at mosta predefined number of writes after the current write.

If DTPA is asserted and the Link Layer device is ready to write a word, it should assert TSX, deassertTENB and present the port address on the TDAT bus if required. Subsequent data transfers withTENB low are treated as packet data which is written to the selected FIFO. At any time, if the LinkLayer device does not have data to write, it can deassert TENB. The TSOP and TEOP signals mustbe appropriately marked at the start and end of packets on the TDAT bus.

Figure 6.1: Transmit Logical Timing

TFCLKTENBTSOPTEOPTMOD[1:0]

TERRTSX

TDAT[31:0]

TPRTYSTPADTPA[0]DTPA[1]

0000B1-B4 B5-B8B41-B44B45-B48B49-B52B53-B56B570001B1-B4When DTPA transitions low and it has been sampled, the Link Layer device can write no more than apredefined number of bytes to the selected FIFO. In this example, the predefined value is two double-words or eight bytes. If the Link Layer writes more than that predefined number of words and DTPAremains deasserted throughout, the PHY layer device should indicate an error condition and ignoreadditional writes until it asserts DTPA again.

Page 18 of 30ATM Technical Committee

af-phy-0143.000March 2000

Frame Based ATM Interface (Level 3)

Figure 6.2 is an example of the Link Layer device using the polling feature of the Transmit Interface.For comparison purposes, the direct transmit packet available signals for the example ports areprovided in the diagram. The status of a given PHY port may be determined by setting the pollingaddress TADR bus to the port address. The polled transmit packet available signal PTPA is updatedwith the transmit FIFO status in a pipelined manner. The Link Layer device is not restricted in its

polling order. The selected transmit packet available STPA signal allows monitoring the selected PHYstatus and halting data transfer once the FIFO is full. The PTPA signal allows polling other PHY’s atany time, including while a data transfer is in progress. The system could be configured differently.

Figure 6.2: Packet-Level Transmit Polling Logical TimingTFCLKTADR[n:0]PTPADTPA[0]DTPA[1]DTPA[2]DTPA[3]P0P1P0P2P1P3P2P3P0P3P1P0P2P1P0P2P1P0P2P1P3P2P3Figure 6.3 shows an example of data transfer to a single-port PHY device without the use of in-bandaddressing, which is optional for single-port applications. During packet transfer, the Link Layer devicepauses for its own internal reasons. As in Figure 6.1, the PHY device indicates its FIFO status bymeans of DTPA.Figure 6.3: Transmit Logical Timing(single-port example without in-band addressing)TFCLKTENBTSOPTEOPTMOD[1:0]TERRTDAT[31:0]TPRTYDTPAB1-B4B5-B8B41-B44B45-B48B49-B52B53-B56B57B1-B4Page 19 of 30ATM Technical Committee

af-phy-0143.000Frame Based ATM Interface (Level 3)

March 2000

6.3AC Timing

All AC Timing is from the perspective of the PHY layer device in a PHY-LINK interface.

Table 6.2: Transmit Interface Timing

Symbol

Description

MinMax

Units

TFCLK Frequency104MHzTFCLK Duty Cycle

4060

%tStenbTENB Set-up time to TFCLK2nstHtenbTENB Hold time to TFCLK0.5nstStdatTDAT[15:0] Set-up time to TFCLK2nstHtdatTDAT[15:0] Hold time to TFCLK0.5nstStprtyTPRTY Set-up time to TFCLK2nstHtprtyTPRTY Hold time to TFCLK0.5nstStsopTSOP Set-up time to TFCLK2nstHtsopTSOP Hold time to TFCLK0.5nstSteopTEOP Set-up time to TFCLK2nstHteopTEOP Hold time to TFCLK0.5nstStmodTMOD Set-up time to TFCLK2nstHtmodTMOD Hold time to TFCLK0.5nstSterrTERR Set-up time to TFCLK2nstHterrTERR Hold time to TFCLK0.5nstStsxTSX Set-up time to TFCLK2nstHtsxTSX Hold time to TFCLK0.5nstStadrTADR[4:0] Set-up time to TFCLK2nstHtadrTADR[4:0] Hold time to TFCLK0.5nstPdtpaTFCLK High to DTPA Valid1.56nstPstpaTFCLK High to STPA Valid1.56nstPptpa

TFCLK High to PTPA Valid

1.5

6

ns

Page 20 of 30ATM Technical Committee

af-phy-0143.000March 2000

Frame Based ATM Interface (Level 3)

Figure 6.3. Transmit Physical Timing

TFCLK

tStenbTENB

tStdatTDAT[31:0]

tStprtyTPRTY

tStsopTSOP

tSteopTEOP

tStmodTMOD[1:0]

tSterrTERR

tStsxTSX

tStadrTADR[]

tPdtpaDTPA[]

tPstpaSTPA

tPptpaPTPA

tHtadrtHtsxtHterrtHtmodtHteoptHtsoptHtprtytHtdattHtenb Notes on Transmit I/O Timing: When a set-up time is specified between an input and a clock, the set-up time is the time

in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.When a hold time is specified between an input and a clock, the hold time is the time innanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of thereference signal to the 1.4 Volt point of the output.

Maximum output propagation delays are measured with a 30 pF load on the outputs.

Note 1:Note 2:Note 3:Note 4:

Page 21 of 30ATM Technical Committee

af-phy-0143.000March 2000

Frame Based ATM Interface (Level 3)

7Receive Packet Interface Description

The standard FIFO depth for interfaces is 256 octets. As the interface is point-to-point, the PHYdevice is required to push receive packet data to the Link Layer device. This arrangement simplifiesthe interface between the PHY device and the Link Layer device. Traditional polling schemes for thereceive side are not required, saving a significant number of pins.

The receive FIFO shall have a programmable threshold defined in terms of the number of bytes ofpacket data stored in the FIFO. A multi-port PHY device must service each receive FIFO with

sufficient packet data to exceed the threshold or with an end of packet. The PHY should service therequired FIFOs in a round-robin fashion. The type of round-robin algorithm will depend on the variousdata rates supported by the PHY device and is outside this specification.

The amount of packet data transferred, when servicing the receive FIFO, is bounded by the FIFO’sprogrammable threshold. Thus, a transfer is limited to a maximum of 256 bytes of data (64 cycles fora 32-bit interface or 256 cycles for an 8-bit interface) or until an end of packet is transferred to theLayer device. At the end of a transfer, the PHY device will round-robin to the next receive FIFO.The PHY device should support a programmable minimum pause of 0 or 2 clock cycles betweentransfers. A pause of 0 clock cycles maximizes the throughput of the interface. A pause of 2 clockcycles allows the Layer device to pause between transfers.

7.1Receive Signals

Table 7.1 lists the receive side signals. All signals are expected to be updated and sampled using therising edge of the receive FIFO clock, RFCLK. A fully compatible POS-PHY Physical Layer devicerequires at least a 256-byte receive FIFO.

Table 7.1: Receive Signal Descriptions

Signal Name

RFCLK

Direction

Clock Sourceto Link andPHY

Function

Receive FIFO Write Clock (RFCLK).

RFCLK is used to synchronize data transfer transactionsbetween the Link Layer device and the PHY layer device.RFCLK may cycle at a rate up to 104 MHz.Receive Data Valid (RVAL) signal.

RVAL indicates the validity of the receive data signals. RVAL islow between transfers and when RSX is asserted; it is also lowwhen the PHY pauses a transfer due to an empty receive FIFO.When a transfer is paused by holding RENB high, RVAL willholds its value unchanged, although no new data will be presenton RDAT[31:0] until the transfer resumes.

When RVAL is high, the RDAT[31:0], RMOD[1:0], RSOP, REOPand RERR signals are valid. When RVAL is low, the

RDAT[31:0], RMOD[1:0], RSOP, REOP and RERR signals areinvalid and must be disregarded.

The RSX signal is valid when RVAL is low.

RVALPHY to LINK

.

Page 22 of 30ATM Technical Committee

af-phy-0143.000March 2000

Frame Based ATM Interface (Level 3)

Signal Name

RENB

Direction

LINK to PHY

Function

Receive Read Enable (RENB) signal.

The RENB signal is used to control the flow of data from thereceive FIFO’s. During data transfer, RVAL must be monitoredas it will indicate if the RDAT[31:0], RPRTY, RMOD[1:0], RSOP,REOP, RERR and RSX are valid. The system may deassertRENB at anytime if it is unable to accept data from the PHYdevice.

When RENB is sampled low by the PHY device, a read is

performed from the receive FIFO and the RDAT[31:0], RPRTY,RMOD[1:0], RSOP, REOP, RERR, RSX and RVAL signals areupdated on the following rising edge of RFCLK.

When RENB is sampled high by the PHY device, a read is notperformed and the RDAT[31:0], RPRTY, RMOD[1:0], RSOP,REOP, RERR, RSX and RVAL signals will remain unchanged onthe following rising edge of RFCLK.

RDAT[31:0]PHY to LINK

Receive Packet Data Bus (RDAT[31:0]).

The RDAT[31:0] bus carries the packet octets that are read fromthe receive FIFO and the in-band port address of the selectedreceive FIFO. RDAT[31:0] is considered valid only when RVALis asserted

When a 32-bit interface is used, data must be received in bigendian order on RDAT[31:0]. Given the defined data structure,bit 31 is received first and bit 0 is received last.When an 8-bit interface is used, the PHY supports onlyRDAT[7:0].

RPRTYPHY to LINK

Receive Parity (RPRTY) signal.

The receive parity (RPRTY) signal indicates the parity calculatedover the RDAT bus. When an 8-bit interface is used, the PHYonly supports RPRTY calculated over RDAT[7:0].

When RPRTY is supported, the PHY layer device must supportodd parity. RPRTY is considered valid only when RVAL or RSXis asserted.

Page 23 of 30ATM Technical Committee

af-phy-0143.000March 2000

Frame Based ATM Interface (Level 3)

Signal Name

RMOD[1:0]

Direction

PHY to LINK

Function

Receive Word Modulo (RMOD) signal.

RMOD[1:0] indicates the number of valid bytes of data in

RDAT[31:0]. The RMOD bus should always be all zero, exceptduring the last double-word transfer of a packet on RDAT[31:0].When REOP is asserted, the number of valid packet data byteson RDAT[31:0] is specified by RMOD[1:0].

RMOD[1:0] = “00”RMOD[1:0] = “01”RMOD[1:0] = “10”RMOD[1:0] = “11”

RDAT[31:0] validRDAT[31:8] validRDAT[31:16] validRDAT[31:24] valid

When an 8-bit interface is used, the RMOD bus is not required.RMOD[1:0] is considered valid only when RVAL is asserted.

RSOP

PHY to LINK

Receive Start of Packet (RSOP) signal.

RSOP is used to delineate the packet boundaries on the RDATbus. When RSOP is high, the start of the packet is present onthe RDAT bus.

RSOP is required to be present at the start of every packet andis considered valid when RVAL is asserted.

REOP

PHY to LINK

Receive End Of Packet (REOP) signal.

REOP is used to delineate the packet boundaries on the RDATbus. When REOP is high, the end of the packet is present onthe RDAT bus.

When a 32-bit interface is used, RMOD[1:0] indicates the

number of valid bytes the last double-word is composed of whenREOP is asserted. When an 8-bit interface is used, the last byteof the packet is on RDAT[7:0] when REOP is asserted.

REOP is required to be present at the end of every packet and isconsidered valid only when RVAL is asserted.

RERR

PHY to LINK

Receive error indicator (RERR) signal.

RERR is used to indicate that the current packet is in error.RERR shall only be asserted when REOP is asserted.Conditions that can cause RERR to be set may be, but are notlimited to, FIFO overflow, abort sequence detection and FCSerror.

RERR is considered valid only when RVAL is asserted.

Page 24 of 30ATM Technical Committee

af-phy-0143.000March 2000

Frame Based ATM Interface (Level 3)

Signal Name

RSX

Direction

PHY to LINK

Function

Receive Start of Transfer (RSX) signal.

RSX indicates when the in-band port address is present on theRDAT bus. When RSX is high, the value of RDAT[7:0] is theaddress of the receive FIFO to be selected by the PHY.

Subsequent data transfers on the RDAT bus will be from theFIFO specified by this in-band address.

For single port PHY devices, the RSX signal is optional as thePHY device will not need to generate in-band addresses.For multi-port PHY devices, RSX must be asserted at thebeginning of each transfer.

When RSX is high, RVAL must be low.

Page 25 of 30ATM Technical Committee

af-phy-0143.000March 2000

Frame Based ATM Interface (Level 3)

7.2Examples

The following examples are not part of the requirement definition of this specification. They are onlyinformative and provide an aid in the visualization of the interface operation. These examples onlypresent a limited set of scenarios; they are not intended to imply restrictions beyond that presented inthe text of the specification. If any apparent discrepancies exist between the examples and the text,the text shall take precedence.

The Receive Interface is controlled by the Link Layer device using the RENB signal. All signals mustbe updated and sampled using the rising edge of the receive FIFO clock. The RDAT bus, RPRTY,RMOD, RSOP, REOP and RERR signals are valid in cycles for which RVAL is high and RENB waslow in the previous cycle. When transferring data, RVAL is asserted and remains high until theinternal FIFO of the PHY layer device is empty or an end of packet is transferred. The RSX signal isvalid in the cycle for which RVAL is low and RENB was low in the previous cycle.

Figure 7.1 is an example of a multi-port PHY device with at least two channels. The PHY informs theLink Layer device of the port address of the selected FIFO by asserting RSX with the port address onthe RDAT bus. The Link Layer may pause the Receive Interface at any time by deasserting theRENB signal. When the selected FIFO is empty, RVAL is deasserted. In this example, the RVAL isre-asserted, without changing the selected FIFO, transferring the last section of the packet. The endof the packet is indicated with the REOP signal. Thus, the next subsequent FIFO transfer for this portwould be the start of the next packet. If an error occurred during the reception of the packet, theRERR would be asserted with REOP. Since another port’s FIFO has sufficient data to initiate a bustransfer, RSX is again asserted with the port address. In this case, an intermediate section of thepacket is being transferred.

Figure 7.1: Receive Logical Timing

RFCLKRENBRSXRSOPREOPRERRRMOD[1:0]RDAT[31:0]

RPRTYRVAL

0000B1-B4B5-B8B9-B12B41-B44B45-B48 B52-B55B56-B570001B21-B25Page 26 of 30ATM Technical Committee

af-phy-0143.000March 2000

Frame Based ATM Interface (Level 3)

Figure 7.2 is an example of a multi-port PHY configured to gap transfers for two clock cycles. Thefirst transfer is a complete 3-byte packet and the second transfer is the end of a 36-byte packet. Thepause allows the Link Layer device to halt the transfer of data between transfers. In order to handlean end of packet, the Link Layer device may deassert the RENB signal when it samples REOP active.As shown in the diagram, the Link Layer device pauses the PHY device on the in-band address fortwo clock cycles.

Figure 7.2: Receive Logical Timing with Pausing

RFCLKRENBRSXRSOPREOPRERRRDAT[7:0]RPRTYRVAL

03B1B2B301B33B34B35B36 Page 27 of 30ATM Technical Committee

af-phy-0143.000March 2000

Frame Based ATM Interface (Level 3)

Figure 7.3 shows an example of data transfer from a single-port PHY device, without the use of the RSXsignal and in-band addressing, which are optional for single-port applications. Just before reaching end-of-packet, the PHY device happens to pause for two cycles (for internal reasons).

Figure 7.3: Receive Logical Timing(single-port without in-band addressing)

RFCLKRENBRSOPREOPRMOD[1:0]

RERRRDAT[31:0]

RPRTYRVAL

B1-B4B5-B8B9-B12B41-B44B45-B48B49B1-B4Page 28 of 30ATM Technical Committee

af-phy-0143.000Frame Based ATM Interface (Level 3)

March 2000

7.3AC Timing

All AC Timing is from the perspective of the PHY layer device in a PHY-LINK interface.

Table 7.3: Receive Interface Timing

Symbol

Description

MinMax

Units

RFCLK Frequency104MHzRFCLK Duty Cycle

4060

%tSrenbRENB Set-up time to RFCLK2nstHrenbRENB Hold time to RFCLK0.5nstPrdatRFCLK High to RDAT Valid1.56nstPrprtyRFCLK High to RPRTY Valid1.56nstPrsopRFCLK High to RSOP Valid1.56nstPreopRFCLK High to REOP Valid1.56nstPrmodRFCLK High to RMOD Valid1.56nstPrerrRFCLK High to RERR Valid1.56nstPrvalRFCLK High to RVAL Valid1.56nstPrsx

RFCLK High to RSX Valid

1.5

6

ns

Page 29 of 30ATM Technical Committee

af-phy-0143.000March 2000

Frame Based ATM Interface (Level 3)

Figure 7.4: Receive Physical Timing

RFCLK

tSrenbRENB

tPrdatRDAT[31:0]

tPrprtyRPRTY

tPrmodRMOD

tPrsopRSOP

tPreopREOP

tPrerrRERR

tPrvalRVAL

tPrsxRSX

tHrenbNotes on Receive I/O Timing:Note 1:

Note 2:Note 3:Note 4:

When a set-up time is specified between an input and a clock, the set-up time is the timein nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.When a hold time is specified between an input and a clock, the hold time is the time innanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of thereference signal to the 1.4 Volt point of the output.

Maximum output propagation delays are measured with a 30 pF load on the outputs.

Page 30 of 30ATM Technical Committee