Clock recovery circuit

专利名称：Clock recovery circuit发明人：Koji Fukuda,Hiroki Yamashita申请号：US12320573申请日：20090129公开号：US08149973B2公开日：20120403

专利附图：

摘要：A clock recovery circuit capable of simultaneously satisfying all of a bit

synchronization period, a clock wander tracking performance, and a high high-frequencyjitter tolerance. The clock recovery circuit includes: a phase difference detecting circuitthat detects a phase difference between an input data signal and a recovery clock; an

averaging circuit that averages the output of the phase difference detecting circuit; asampling and holding circuit with resetting that samples and holds the output of thephase difference detecting circuit; and a recovery clock generating circuit that generatesa recovery clock having a phase corresponding to the sum of the integral value of theoutput of the averaging circuit and the output of the sampling and holding circuit withresetting. The sampling and holding circuit with resetting receives a burst transmissionstart signal and samples and holds the output of the phase difference detecting. Inaddition, the sampling and holding circuit with resetting receives a burst transmission endsignal and resets the held value to an initial value.

申请人：Koji Fukuda,Hiroki Yamashita

地址：Fuchu JP,Hachioji JP

国籍：JP,JP

代理机构：Stites & Harbison, PLLC

代理人：Juan Carlos A. Marquez, Esq.

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