When AMIBIOS performs the Power On Self Test, it writes diagnostic codes checkpointcodes to I/O port 0080h. If the computer cannot complete the boot process, diagnosticequipment can be attached to the computer to read I/O port 0080h. The following
AMIBIOS POST checkpoint codes are valid for all AMIBIOS products with a core BIOSdate of 7/15/95.
6.1 Uncompressed Initialization Codes
order of execution:
CheckpointCodeD0h
D1hD3hD4hD5hD6h
The uncompressed initialization checkpoint codes are listed in
Description
The NMI is disabled. Power on delay is starting. Next, the initializationcode checksum will be verified.
Initializing the DMA controller, performing the keyboard controller BATtest, starting memory refresh, and entering 4 GB flat mode next.Starting memory sizing next.
Returning to real mode. Executing any OEM patches and setting the stacknext.
Passing control to the uncompressed code in shadow RAM at
E000:0000h.The initialization code is copied to segment 0 and control willbe transferred to segment 0.
Control is in segment 0. Next, checking if If either Cont’d POST Checkpoint Codes, Continued6.2 Bootblock Recovery Codes execution: CheckpointCodeE0h E1hE2hE6hEdhEehEfhF0hF1hF2hF3hF4hF5hFBhFChFDhFFh The bootblock recovery checkpoint codes are listed in order of Description The onboard floppy controller if available is initialized. Next, beginning thebase 512 KB memory test. Initializing the interrupt vector table next. Initializing the DMA and Interrupt controllers next. Enabling the floppy drive controller and Timer IRQs. Enabling internal cachememory. Initializing the floppy drive. Looking for a floppy diskette in drive A:. Reading the first sector of thediskette. A read error occurred while reading the floppy drive in drive A:.Next, searching for the AMIBOOT.ROM file in the root directory.The AMIBOOT.ROM file is not in the root directory. Next, reading and analyzing the floppy diskette FAT to find the clustersoccupied by the AMIBOOT.ROM file. Next, reading the AMIBOOT.ROM file, cluster by cluster.The AMIBOOT.ROM file is not the correct size.Next, disabling internal cache memory.Next, detecting the type of flash ROM.Next, erasing the flash ROM. Next, programming the flash ROM. Flash ROM programming was successful. Next, restarting the system BIOS. 6.3 Uncompressed Initialization CodesThe following runtime checkpoint codes are listed in order of execution. These codes are uncompressed in F0000h shadow RAM. CheckpointCode03h05h06h07h08h0Ah 0Bh0Ch0Eh0Fh10h11h Description The NMI is disabled. Next, checking for a soft reset or a power on condition.The BIOS stack has been built. Next, disabling cache memory.Uncompressing the POST code next. Next, initializing the CPU and the CPU data area.The CMOS checksum calculation is done next. The CMOS checksum calculation is done. Initializing the CMOS statusregister for date and time next. The CMOS status register is initialized. Next, performing any requiredinitialization before the keyboard BAT command is issued. The keyboard controller input buffer is free. Next, issuing the BATcommand to the keyboard controller. The keyboard controller BAT command result has been verified. Next,performing any necessary initialization after the keyboard controller BATcommand test. The initialization after the keyboard controller BAT command test is done.The keyboard command byte is written next. The keyboard controller command byte is written. Next, issuing the Pin 23and 24 blocking and unblocking command. Next, checking if AMIBIOS POST option was set in AMIBCP or the The 8254 timer test will begin next. The 8254 timer test is over. Starting the memory refresh test next. The memory refresh line is toggling. Checking the 15 second on/off timenext. 12h13h14h19h1Ah CheckpointCode23h 24h25h27h28h2Ah2Bh2Ch2Dh2Eh2Fh30h31h32h34h37h38h39h3Ah3Bh40h42h43h44h45h46h47h48h49h4Bh Description Reading the 8042 input port and disabling the MEGAKEY Green PC featurenext. Making the BIOS code segment writable and performing any necessaryconfiguration before initializing the interrupt vectors. The configuration required before interrupt vector initialization hascompleted. Interrupt vector initialization is about to begin. Interrupt vector initialization is done. Clearing the password if the POSTDIAG switch is on. Any initialization before setting video mode will be done next. Initialization before setting the video mode is complete. Configuring themonochrome mode and color mode settings next. Bus initialization system, static, output devices will be done next, if present.See page 6 for additional information. Passing control to the video ROM to perform any required configurationbefore the video ROM test. All necessary processing before passing control to the video ROM is done.Looking for the video ROM next and passing control to it. The video ROM has returned control to BIOS POST. Performing anyrequired processing after the video ROM had control. Completed post-video ROM test processing. If the EGA/VGA controller isnot found, performing the display memory read/write test next. The EGA/VGA controller was not found. The display memory read/writetest is about to begin. The display memory read/write test passed. Look for retrace checking next.The display memory read/write test or retrace checking failed. Performingthe alternate display memory read/write test next. The alternate display memory read/write test passed. Looking for alternatedisplay retrace checking next. Video display checking is over. Setting the display mode next.The display mode is set. Displaying the power on message next. Initializing the bus input, IPL, general devices next, if present. See page 6 foradditional information. Displaying bus initialization error messages. See page 6 for additionalinformation. The new cursor position has been read and saved. Displaying the Hit The Hit Preparing the descriptor tables next. The descriptor tables are prepared. Entering protected mode for the memorytest next. Entered protected mode. Enabling interrupts for diagnostics mode next.Interrupts enabled if the diagnostics switch is on. Initializing data to checkmemory wraparound at 0:0 next. Data initialized. Checking for memory wraparound at 0:0 and finding thetotal system memory size next. The memory wraparound test is done. Memory size calculation has beendone. Writing patterns to test memory next. The memory pattern has been written to extended memory. Writing patternsto the base 640 KB memory next. Patterns written in base memory. Determining the amount of memory below1 MB next. The amount of memory below 1 MB has been found and verified.Determining the amount of memory above 1 MB memory next. The amount of memory above 1 MB has been found and verified. Checkingfor a soft reset and clearing the memory below 1 MB for the soft reset next.If this is a power on situation, going to checkpoint 4Eh next. The memory below 1 MB has been cleared via a soft reset. Clearing thememory above 1 MB next. The memory above 1 MB has been cleared via a soft reset. Saving thememory size next. Going to checkpoint 52h next. The memory test started, but not as the result of a soft reset. Displaying thefirst 64 KB memory size next. The memory size display has started. The display is updated during thememory test. Performing the sequential and random memory test next. 4Ch4Dh4Eh4Fh CheckpointCode50h 51h52h53h54h57h58h59h60h62h65h66h67h7Fh80h81h82h83h84h85h86h87h88h89h8Bh8Ch8Dh8Fh91h95h96h97h98h Description The memory below 1 MB has been tested and initialized. Adjusting thedisplayed memory size for relocation and shadowing next. The memory size display was adjusted for relocation and shadowing. Testingthe memory above 1 MB next. The memory above 1 MB has been tested and initialized. Saving the memorysize information next. The memory size information and the CPU registers are saved. Entering realmode next. Shutdown was successful. The CPU is in real mode. Disabling the Gate A20line, parity, and the NMI next. The A20 address line, parity, and the NMI are disabled. Adjusting thememory size depending on relocation and shadowing next. The memory size was adjusted for relocation and shadowing. Clearing theHit The Hit The DMA page register test passed. Performing the DMA Controller 1 baseregister test next. The DMA controller 1 base register test passed. Performing the DMAcontroller 2 base register test next. The DMA controller 2 base register test passed. Programming DMAcontrollers 1 and 2 next. Completed programming DMA controllers 1 and 2. Initializing the 8259interrupt controller next. Completed 8259 interrupt controller initialization.Extended NMI source enabling is in progress. The keyboard test has started. Clearing the output buffer and checking forstuck keys. Issuing the keyboard reset command next. A keyboard reset error or stuck key was found. Issuing the keyboardcontroller interface test command next. The keyboard controller interface test completed. Writing the command byteand initializing the circular buffer next. The command byte was written and global data initialization has completed.Checking for a locked key next. Locked key checking is over. Checking for a memory size mismatch withCMOS RAM data next. The memory size check is done. Displaying a soft error and checking for apassword or bypassing WINBIOS Setup next. The password was checked. Performing any required programming beforeWINBIOS Setup next. The programming before WINBIOS Setup has completed. Uncompressingthe WINBIOS Setup code and executing the AMIBIOS Setup or WINBIOSSetup utility next. Returned from WINBIOS Setup and cleared the screen. Performing anynecessary programming after WINBIOS Setup next. The programming after WINBIOS Setup has completed. Displaying thepower on screen message next. The first screen message has been displayed. The Programming the WINBIOS Setup options next. The WINBIOS Setup options are programmed. Resetting the hard diskcontroller next. The hard disk controller has been reset. Configuring the floppy drivecontroller next. The floppy drive controller has been configured. Configuring the hard diskdrive controller next. Initializing the bus option ROMs from C800 next. See page 6 for additionalinformation. Initializing before passing control to the adaptor ROM at C800. Initialization before the C800 adaptor ROM gains control has completed.The adaptor ROM check is next. The adaptor ROM had control and has now returned control to BIOS POST.Performing any required processing after the option ROM returned control. CheckpointCode99h 9Ah9Bh9Ch9Dh9EhA2hA3hA4hA5hA7hA8hA9hAahAbhB0hB1h00h Description Any initialization required after the option ROM test has completed.Configuring the timer data area and printer base address next. Set the timer and printer base addresses. Setting the RS-232 base addressnext. Returned after setting the RS-232 base address. Performing any requiredinitialization before the Coprocessor test next. Required initialization before the Coprocessor test is over. Initializing theCoprocessor next. Coprocessor initialized. Performing any required initialization after theCoprocessor test next. Initialization after the Coprocessor test is complete. Checking the extendedkeyboard, keyboard ID, and Num Lock key next. Issuing the keyboard IDcommand next. Displaying any soft errors next. The soft error display has completed. Setting the keyboard typematic ratenext. The keyboard typematic rate is set. Programming the memory wait statesnext. Memory wait state programming is over. Clearing the screen and enablingparity and the NMI next. NMI and parity enabled. Performing any initialization required beforepassing control to the adaptor ROM at E000 next. Initialization before passing control to the adaptor ROM at E000h completed.Passing control to the adaptor ROM at E000h next. Returned from adaptor ROM at E000h control. Performing any initializationrequired after the E000 option ROM had control next. Initialization after E000 option ROM control has completed. Displaying thesystem configuration next. Uncompressing the DMI data and executing DMI POST initialization next.The system configuration is displayed.Copying any code to specific areas. Code copying to specific areas is done. Passing control to INT 19h bootloader next. 6.4 Bus Checkpoint Codes The system BIOS passes control to different buses at the following checkpoints: CheckpointCode2Ah38h39h95h Description Initializing the different bus system, static, and output devices, if present.Initialized bus input, IPL, and general devices, if present.Displaying bus initialization error messages, if any. Initializing bus adaptor ROMs from C8000h through D8000h. Additional Bus CheckpointsWhile control is inside the different bus routines, additional checkpoints are output to I/O port address 0080h as word to identify the routines beingexecuted. These are word checkpoints. The low byte of checkpoint is the system BIOS checkpointwhere control is passed to the different bus routines. The high byte of checkpoint indicates that the routine is being executed in differentbuses. High Byte BitsBits 7-4 The high byte of these checkpoints includes the following information: Description 0000Function 0. Disable all devices on the bus.0001Function 1. Initialize static devices on the bus.0010Function 2. Initialize output devices on the bus.0011Function 3. Initialize input devices on the bus.0100Function 4. Initialize IPL devices on the bus.0101Function 5. Initiate general devices on the bus.0110Function 6. Initialize error reporting on the bus.0111Function 7. Initialize add-on ROMs for all buses.Specify the bus012345 Generic DIM Device Initialization Manager.Onboard System devices.ISA devices.EISA devices.ISA PnP devices.PCI devices. Bits 3-0 因篇幅问题不能全部显示，请点此查看更多更全内容message next. message is displayed. The protected mode memory test isabout to start. message next. message is cleared. The