PORT ( a, b, s: IN BIT; y : OUT BIT ); END ENTITY mux21a;
ARCHITECTURE one OF mux21a IS BEGIN
PROCESS (a,b,s) BEGIN
IF s = '0' THEN y <= a ; ELSE y <= b ; END IF;
END PROCESS;
END ARCHITECTURE one ;
实验2—— D触发器VHDL描述 LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ; ENTITY DFF1 IS
PORT (CLK : IN STD_LOGIC ; D : IN STD_LOGIC ; Q : OUT STD_LOGIC ); END ;
ARCHITECTURE bhv OF DFF1 IS
SIGNAL Q1 : STD_LOGIC ; --类似于在芯片内部定义一个数据的暂存节点 BEGIN
PROCESS (CLK,Q1) BEGIN
IF CLK'EVENT AND CLK = '1' THEN Q1 <= D ; END IF; END PROCESS ;
Q <= Q1 ; --将内部暂存数据向端口输出（双横线--是注释符号） END bhv;
实验3—— 半加器VHDL描述
LIBRARY IEEE; --半加器描述(1)：布尔方程描述方法 USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_adder IS
PORT (a, b : IN STD_LOGIC; co, so : OUT STD_LOGIC); END ENTITY h_adder;
ARCHITECTURE fh1 OF h_adder is BEGIN
so <= NOT(a XOR (NOT b)) ; co <= a AND b ; END ARCHITECTURE fh1;
实验4—— 全加器VHDL描述
LIBRARY IEEE; --1位二进制全加器顶层设计描述 USE IEEE.STD_LOGIC_1164.ALL; ENTITY f_adder IS
PORT (ain，bin，cin : IN STD_LOGIC;
cout，sum : OUT STD_LOGIC ); END ENTITY f_adder;
ARCHITECTURE fd1 OF f_adder IS
COMPONENT h_adder --调用半加器声明语句 PORT ( a，b : IN STD_LOGIC; co，so : OUT STD_LOGIC); END COMPONENT ； COMPONENT or2a
PORT (a，b : IN STD_LOGIC; c : OUT STD_LOGIC); END COMPONENT；
SIGNAL d，e，f : STD_LOGIC; --定义3个信号作为内部的连接线。 BEGIN
u1 : h_adder PORT MAP(a=>ain，b=>bin，co=>d，so=>e); --例化语句 u2 : h_adder PORT MAP(a=>e， b=>cin， co=>f，so=>sum); u3 : or2a PORT MAP(a=>d， b=>f， c=>cout); END ARCHITECTURE fd1;
实验5——方波发生器VHDL程序（简易函数发生器设计1）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY square IS
PORT(clk,reset:IN STD_LOGIC;
q:OUT STD_LOGIC); END square;
ARCHITECTURE bhv OF square IS
BEGIN
PROCESS(clk,reset)
VARIABLE cnt:INTEGER RANGE 0 TO 63; BEGIN
IF reset='0' THEN q<='0';
ELSIF clk'EVENT AND clk='1' THEN cnt:=cnt+1;
IF cnt<31 THEN
q<='0'; ELSE
q<='1'; END IF; END IF;
END PROCESS;
END bhv;
实验6 — 正弦波发生器VHDL程序（简易函数发生器设计2） LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY sin IS
PORT(clk,reset:IN STD_LOGIC; q:OUT INTEGER RANGE 0 TO 255); END sin;
ARCHITECTURE bhv OF sin IS BEGIN
PROCESS(clk,reset)
VARIABLE tmp:INTEGER RANGE 0 TO 63; BEGIN
IF reset='0' THEN q<=0;
ELSIF clk'EVENT AND clk='1' THEN IF tmp=63 THEN tmp:=0; ELSE tmp:=tmp+1; END IF; CASE tmp IS WHEN 00=>q<=255; WHEN 01=>q<=254; WHEN 02=>q<=252;
WHEN 03=>q<=249; WHEN 04=>q<=245; WHEN 05=>q<=239; WHEN 06=>q<=233; WHEN 07=>q<=225; WHEN 08=>q<=217; WHEN 09=>q<=207; WHEN 10=>q<=197; WHEN 11=>q<=186; WHEN 12=>q<=174; WHEN 13=>q<=162; WHEN 14=>q<=150; WHEN 15=>q<=137; WHEN 16=>q<=124; WHEN 17=>q<=112; WHEN 18=>q<=99; WHEN 19=>q<=87; WHEN 20=>q<=75; WHEN 21=>q<=64; WHEN 22=>q<=53; WHEN 23=>q<=43; WHEN 24=>q<=34; WHEN 25=>q<=26; WHEN 26=>q<=19; WHEN 27=>q<=13; WHEN 28=>q<=8; WHEN 29=>q<=4; WHEN 30=>q<=1; WHEN 31=>q<=0; WHEN 32=>q<=0; WHEN 33=>q<=1; WHEN 34=>q<=4; WHEN 35=>q<=8; WHEN 36=>q<=13; WHEN 37=>q<=19; WHEN 38=>q<=26; WHEN 39=>q<=34; WHEN 40=>q<=43;
WHEN 41=>q<=53; WHEN 42=>q<=64; WHEN 43=>q<=75; WHEN 44=>q<=87; WHEN 45=>q<=99; WHEN 46=>q<=112; WHEN 47=>q<=124; WHEN 48=>q<=137; WHEN 49=>q<=150; WHEN 50=>q<=162; WHEN 51=>q<=174; WHEN 52=>q<=186; WHEN 53=>q<=197; WHEN 54=>q<=207; WHEN 55=>q<=217; WHEN 56=>q<=225; WHEN 57=>q<=233; WHEN 58=>q<=239; WHEN 59=>q<=245; WHEN 60=>q<=249; WHEN 61=>q<=252; WHEN 62=>q<=254; WHEN 63=>q<=255; WHEN OTHERS=>NULL; END CASE; END IF; END PROCESS;
END bhv;
实验8 —— 三选一数据选择器VHDL LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; entity selection31 is
port(a,b,c,d:in STD_LOGIC_vector(1 downto 0); s:in STD_LOGIC_VECTOR(1 downto 0); y:out STD_LOGIC_vector(1 downto 0)); end entity selection31;
architecture arc of selection31 is begin
process(a,b,c,d) begin
if s=\"00\" then y<=a;
elsif s=\"01\" then y<=b;
elsif s=\"10\" then y<=c; else y<=d; end if; end process;
end architecture arc;
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