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ATTINY12L-4SU资料

2021-01-18 来源:爱问旅游网
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Features

•Utilizes the AVR® RISC Architecture

•AVR – High-performance and Low-power RISC Architecture

–90 Powerful Instructions – Most Single Clock Cycle Execution–32 x 8 General-purpose Working Registers–Up to 4 MIPS Throughput at 4 MHzNonvolatile Program Memory

–2K Bytes of Flash Program Memory–Endurance: 1,000 Write/Erase Cycles

–Programming Lock for Flash Program Data SecurityPeripheral Features

–Interrupt and Wake-up on Low-level Input

–One 8-bit Timer/Counter with Separate Prescaler–On-chip Analog Comparator

–Programmable Watchdog Timer with On-chip Oscillator

–Built-in High-current LED Driver with Programmable ModulationSpecial Microcontroller Features

–Low-power Idle and Power-down Modes–External and Internal Interrupt Sources

–Power-on Reset Circuit with Programmable Start-up Time–Internal Calibrated RC OscillatorPower Consumption at 1 MHz, 2V, 25°C–Active: 3.0 mA–Idle Mode: 1.2 mA

–Power-down Mode: <1 µAI/O and Packages

–11 Programmable I/O Lines, 8 Input Lines and a High-current LED Driver–28-lead PDIP, 32-lead TQFP, and 32-pad MLFOperating Voltages

–VCC: 1.8V - 5.5V for the ATtiny28V–VCC: 2.7V - 5.5V for the ATtiny28LSpeed Grades

–0 - 1.2 MHz for the ATtiny28V–0 - 4 MHz For the ATtiny28L

8-bit Microcontroller with 2K Bytes of FlashATtiny28LATtiny28VSummary•

•••

Pin Configurations

PDIP

RESETPD0PD1PD2PD3PD4VCCGNDXTAL1XTAL2PD5PD6PD7(AIN0) PB012345678910111213142827262524232221201918171615PA0PA1PA3PA2 (IR)PB7PB6GNDNCVCCPB5PB4 (INT1)PB3 (INT0)PB2 (T0)PB1 (AIN1)TQFP/QFN/MLF

PD2PD1PD0RESETPA0PA1PA3PA2 (IR)32313029282726252423222120191817910111213141516PD3PD4NCVCCGNDNCXTAL1XTAL212345678PB7PB6NCGNDNCNCVCCPB5PD5PD6PD7(AIN0) PB0(AIN1) PB1(T0) PB2(INT0) PB3(INT1) PB4Rev. 1062FS–AVR–07/06Note: This is a summary document. A complete document

1is available on our Web site at www.atmel.com.

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Description

The ATtiny28 is a low-power CMOS 8-bit microcontroller based on the AVR RISC archi-tecture. By executing powerful instructions in a single clock cycle, the ATtiny28 achievesthroughputs approaching 1 MIPS per MHz, allowing the system designer to optimizepower consumption versus processing speed. The AVR core combines a rich instructionset with 32 general-purpose working registers. All the 32 registers are directly con-nected to the Arithmetic Logic Unit (ALU), allowing two independent registers to beaccessed in one single instruction executed in one clock cycle. The resulting architec-ture is more code efficient while achieving throughputs up to ten times faster thanconventional CISC microcontrollers.Figure 1. The ATtiny28 Block Diagram

VCC8-BIT DATA BUSINTERNALOSCILLATORGNDPROGRAMCOUNTERPROGRAMFLASHINSTRUCTIONREGISTERINSTRUCTIONDECODERCONTROLLINESSTACKPOINTERHARDWARESTACKWATCHDOG TIMERMCU CONTROLREGISTERTIMER/COUNTERINTERRUPTUNITTIMING ANDCONTROLRESETOSCILLATORXTAL1XTAL2INTERNALCALIBRATEDOSCILLATORBlock Diagram

GENERALPURPOSEREGISTERSZALUSTATUSREGISTERPROGRAMMINGLOGICHARDWAREMODULATORANALOGCOMPARATORDATA REGISTERPORTBDATA REGISTERPORTDDATA DIRREG. PORTDDATA REGISTERPORTA CONTROLPORTAREGISTER+-PORTB PORTD PORTA The ATtiny28 provides the following features: 2K bytes of Flash, 11 general-purpose I/Olines, 8 input lines, a high-current LED driver, 32 general-purpose working registers, an8-bit timer/counter, internal and external interrupts, programmable Watchdog Timer withinternal oscillator and 2 software-selectable power-saving modes. The Idle Mode stopsthe CPU while allowing the timer/counter and interrupt system to continue functioning.The Power-down mode saves the register contents but freezes the oscillator, disablingall other chip functions until the next interrupt or hardware reset. The wake-up or inter-

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ATtiny28L/V

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ATtiny28L/V

rupt on low-level input feature enables the ATtiny28 to be highly responsive to externalevents, still featuring the lowest power consumption while in the power-down modes.The device is manufactured using Atmel’s high-density, nonvolatile memory technology.By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the AtmelATtiny28 is a powerful microcontroller that provides a highly flexible and cost-effectivesolution to many embedded control applications. The ATtiny28 AVR is supported with afull suite of program and system development tools including: macro assemblers, pro-gram debugger/simulators, in-circuit emulators and evaluation kits.

Pin Descriptions

VCCGND

Port A (PA3..PA0)

Supply voltage pin.Ground pin.

Port A is a 4-bit I/O port. PA2 is output-only and can be used as a high-current LEDdriver. At VCC = 2.0V, the PA2 output buffer can sink 25 mA. PA3, PA1 and PA0 arebi-directional I/O pins with internal pull-ups (selected for each bit). The port pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port B is an 8-bit input port with internal pull-ups (selected for all Port B pins). Port Bpins that are externally pulled low will source current if the pull-ups are activated.Port B also serves the functions of various special features of the ATtiny28 as listed onpage 27. If any of the special features are enabled, the pull-up(s) on the correspondingpin(s) is automatically disabled. The port pins are tri-stated when a reset conditionbecomes active, even if the clock is not running.

Port D (PD7..PD0)

Port D is an 8-bit I/O port. Port pins can provide internal pull-up resistors (selected foreach bit). The port pins are tri-stated when a reset condition becomes active, even if theclock is not running.

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.Output from the inverting oscillator amplifier.

Reset input. An external reset is generated by a low level on the RESET pin. Resetpulses longer than 50 ns will generate a reset, even if the clock is not running. Shorterpulses are not guaranteed to generate a reset.

Port B (PB7..PB0)

XTAL1XTAL2RESET3

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Register Summary

Address

$3F$3E...$20$1F$1E$1D$1C$1B$1A$19$18$17$16$15$14$13$12$11$10$0F$0E$0D$0C$0B$0A$09$08$07$06$05$04$03$02$01$00

Name

SREGReservedReservedReservedReservedReservedReservedReservedPORTAPACRPINAReservedReservedPINBReservedReservedReservedPORTDDDRDPINDReservedReservedReservedReservedReservedReservedReservedACSRMCUCSICRIFRTCCR0TCNT0MODCRWDTCROSCCAL

Bit 7

I

Bit 6

T

Bit 5

H

Bit 4

S

Bit 3

V

Bit 2

N

Bit 1

Z

Bit 0

C

Page

page 6

---

---

---

---

PORTA3DDA3PINA3

PORTA2PA2HC

-

PORTA1DDA1PINA1

PORTA0DDA0PINA0

page 32page 32page 32

PINB7PINB6PINB5PINB4PINB3PINB2PINB1PINB0page 32

PORTD7DDD7PIND7

PORTD6DDD6PIND6

PORTD5DDD5PIND5

PORTD4DDD4PIND4

PORTD3DDD3PIND3

PORTD2DDD2PIND2

PORTD1DDD1PIND1

PORTD0DDD0PIND0

page 33page 33page 33

ACDPLUPBINT1INTF1FOV0ONTIM4

-

--INT0INTF0-ONTIM3

-

ACOSELLIE--ONTIM2

-

ACISMTOIE0TOV0OOM01ONTIM1 WDTOE

ACIEWDRFISC11-OOM00ONTIM0WDE

--ISC10-CS02MCONF2WDP2

ACIS1EXTRFISC01-CS01MCONF1WDP1

ACIS0PORFISC00-CS00MCONF0WDP0

page 44page 19page 22page 23page 35page 36page 43page 37page 9

Timer/Counter0 (8-bit)

Oscillator Calibration Register

Notes:

1.For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2.Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all

bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions workwith registers $00 to $1F only.

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ATtiny28L/V

Instruction Set Summary

Mnemonic

ADDADCSUBSUBISBCSBCIANDANDIORORIEORCOMNEGSBRCBRINCDECTSTCLRSERRJMPRCALLRETRETICPSECPCPCCPISBRCSBRSSBICSBISBRBSBRBCBREQBRNEBRCSBRCCBRSHBRLOBRMIBRPLBRGEBRLTBRHSBRHCBRTSBRTCBRVSBRVCBRIEBRID

Rd, RrRd, RrRd, RrRd, KRr, bRr, bP, bP, bs, ks, kkkkkkkkkkkkkkkkkkk

Operands

Rd, RrRd, RrRd, RrRd, KRd, RrRd, KRd, RrRd, KRd, RrRd, KRd, RrRdRdRd, KRd, KRdRdRdRdRdkk

Description

Add Two Registers

Add with Carry Two RegistersSubtract Two RegistersSubtract Constant from RegisterSubtract with Carry Two RegistersSubtract with Carry Constant from Reg.Logical AND Registers

Logical AND Register and ConstantLogical OR Registers

Logical OR Register and ConstantExclusive OR RegistersOne’s ComplementTwo’s ComplementSet Bit(s) in RegisterClear Bit(s) in RegisterIncrementDecrement

Test for Zero or MinusClear RegisterSet RegisterRelative Jump

Relative Subroutine CallSubroutine ReturnInterrupt ReturnCompare, Skip if EqualCompare

Compare with Carry

Compare Register with ImmediateSkip if Bit in Register ClearedSkip if Bit in Register is SetSkip if Bit in I/O Register ClearedSkip if Bit in I/O Register is SetBranch if Status Flag SetBranch if Status Flag ClearedBranch if EqualBranch if Not EqualBranch if Carry SetBranch if Carry ClearedBranch if Same or HigherBranch if LowerBranch if MinusBranch if Plus

Branch if Greater or Equal, SignedBranch if Less than Zero, SignedBranch if Half-carry Flag SetBranch if Half-carry Flag ClearedBranch if T-flag SetBranch if T-flag ClearedBranch if Overflow Flag is SetBranch if Overflow Flag is ClearedBranch if Interrupt EnabledBranch if Interrupt Disabled

Operation

Rd ← Rd + RrRd ← Rd + Rr + CRd ← Rd - RrRd ← Rd - KRd ← Rd - Rr - CRd ← Rd - K - CRd ← Rd • RrRd ← Rd • KRd ← Rd v RrRd ← Rd v KRd ← Rd ⊕ RrRd ← $FF - RdRd ← $00 - RdRd ← Rd v KRd ← Rd • (FFh - K)Rd ← Rd + 1Rd ← Rd - 1 Rd ← Rd ⊕ RdRd ← $FFPC ← PC + k + 1PC ← PC + k + 1PC ← STACKPC ← STACK

if (Rd = Rr) PC ← PC + 2 or 3Rd - RrRd - Rr - CRd - K

if (Rr(b) = 0) PC ← PC + 2 or 3if (Rr(b) = 1) PC ← PC + 2 or 3if (P(b) = 0) PC ← PC + 2 or 3if (P(b) = 1) PC ← PC + 2 or 3if (SREG(s) = 1) then PC ← PC + k + 1if (SREG(s) = 0) then PC ← PC + k + 1if (Z = 1) then PC ← PC + k + 1if (Z = 0) then PC ← PC + k + 1if (C = 1) then PC ← PC + k + 1if (C = 0) then PC ← PC + k + 1if (C = 0) then PC ← PC + k + 1if (C = 1) then PC ← PC + k + 1if (N = 1) then PC ← PC + k + 1if (N = 0) then PC ← PC + k + 1if (N ⊕ V = 0) then PC ← PC + k + 1if (N ⊕ V = 1) then PC ← PC + k + 1if (H = 1) then PC ← PC + k + 1if (H = 0) then PC ← PC + k + 1if (T = 1) then PC ← PC + k + 1if (T = 0) then PC ← PC + k + 1if (V = 1) then PC ← PC + k + 1if (V = 0) then PC ← PC + k + 1if (I = 1) then PC ← PC + k + 1if (I = 0) then PC ← PC + k + 1

Flags

Z,C,N,V,HZ,C,N,V,HZ,C,N,V,HZ,C,N,V,HZ,C,N,V,HZ,C,N,V,HZ,N,VZ,N,VZ,N,VZ,N,VZ,N,VZ,C,N,VZ,C,N,V,HZ,N,VZ,N,VZ,N,VZ,N,VZ,N,VNoneNoneNoneNoneINoneZ,N,V,C,HZ,N,V,C,HZ N,V,C,HNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNone

# Clocks

1111111111111111111123441/21111/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/2

ARITHMETIC AND LOGIC INSTRUCTIONS

Rd ← Rd • Rd Z,N,VBRANCH INSTRUCTIONS

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Instruction Set Summary (Continued)

Mnemonic

LDSTMOVLDIINOUTLPM

BIT AND BIT-TEST INSTRUCTIONSSBICBILSLLSRROLRORASRSWAPBSETBCLRBSTBLDSECCLCSENCLNSEZCLZSEICLISESCLSSEVCLVSETCLTSEHCLHNOPSLEEPWDR

P, bP, bRdRdRdRdRdRdssRr, bRd, b

Operands

Rd, ZZ, RrRd, RrRd, KRd, PP, Rr

Description

Load Register IndirectStore Register IndirectMove between RegistersLoad ImmediateIn PortOut Port

Operation

Rd ← (Z)(Z) ← RrRd ← RrRd ←KRd ←P

Flags

NoneNoneNoneNoneNoneNoneNoneNoneNoneZ,C,N,VZ,C,N,VZ,C,N,VZ,C,N,VZ,C,N,VNoneSREG(s)SREG(s)TNoneCCNNZZ

# Clocks

2211113221111111111111111

DATA TRANSFER INSTRUCTIONS

P ← Rr

Load Program MemoryR0 ← (Z) Set Bit in I/O RegisterI/O(P,b) ←1 Clear Bit in I/O RegisterI/O(P,b) ←0 Logical Shift LeftRd(n+1) ← Rd(n), Rd(0) ← 0 Logical Shift RightRd(n) ← Rd(n+1), Rd(7) ← 0 Rotate Left through CarryRd(0) ← C, Rd(n+1) ← Rd(n), C ← Rd(7) Rotate Right through CarryRd(7) ← C, Rd(n) ← Rd(n+1), C ← Rd(0) Arithmetic Shift RightRd(n) ← Rd(n+1), n = 0..6Flag Set

Swap NibblesRd(3..0) ← Rd(7..4), Rd(7..4) ← Rd(3..0) SREG(s) ← 1

Flag ClearSREG(s) ← 0

T ← Rr(b)Rd(b) ←TC ←1C ←0N ← 1

N ←0 Z ←1

Z ←0

Bit Store from Register to TBit Load from T to RegisterSet CarryClear CarrySet Negative FlagClear Negative FlagSet Zero FlagClear Zero Flag

Global Interrupt EnableI ←1

Global Interrupt DisableI ←0 Set Signed Test FlagClear Signed Test Flag

Set Two’s Complement OverflowClear Two’s Complement OverflowSet T in SREGClear T in SREG

Set Half-carry Flag in SREGClear Half-carry Flag in SREGNo OperationSleep

Watchdog Reset

(see specific descr. for Sleep function)(see specific descr. for WDR/timer)S ←1S ←0V ←1V ←0T ←1T ← 0H ←1H ←0

I1SSVVTTHHNoneNoneNone

11111111111

I1

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ATtiny28L/V

Ordering Information

Speed (MHz)

Power Supply (Volts)

Ordering CodeATtiny28L-4ACATtiny28L-4PCATtiny28L-4MC

4

2.7 - 5.5

ATtiny28L-4AIATtiny28L-4AU(2)ATtiny28L-4PIATtiny28L-4PU(2)ATtiny28L-4MIATtiny28L-4MU(2)ATtiny28V-1ACATtiny28V-1PCATtiny28V-1MC

1.2

1.8 - 5.5

ATtiny28V-1AIATtiny28V-1AU(2)ATtiny28V-1PIATtiny28V-1PU(2)ATtiny28V-1MIATtiny28V-1MU(2)

Package(1)32A28P332M1-A32A32A28P328P332M1-A32M1-A32A28P332M1-A32A32A28P328P332M1-A32M1-A

Operation RangeCommercial(0°C to 70°C)

Industrial(-40°C to 85°C)

Commercial(0°C to 70°C)

Industrial(-40°C to 85°C)

Notes:

1.This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2.Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-tive).Also Halide free and fully Green.

Package Type

32A28P332M1-A

32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)28-lead, 0.300\" Wide, Plastic Dual Inline Package (PDIP)

32-pad, 5x5x1.0 body, Lead Pitch 0.50mm, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF)

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Packaging Information

32A

PIN 1 BPIN 1 IDENTIFIEReE1ED1DC0˚~7˚A1A2ACOMMON DIMENSIONS(Unit of Measure = mm)SYMBOLAA1A2DD1Notes:1.This package conforms to JEDEC reference MS-026, Variation ABA. 2.Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch.3. Lead coplanarity is 0.10 mm maximum.EE1MIN–0.05 0.958.756.908.756.90NOM––1.009.007.009.007.00–––0.80 TYPMAX1.200.151.059.257.109.257.100.450.20 0.75Note 2Note 2 NOTELB 0.30CLe0.090.4510/5/2001 2325 Orchard Parkway San Jose, CA 95131TITLE32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness,0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO.32AREV. BR8

ATtiny28L/V

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ATtiny28L/V

28P3

DPIN1E1ASEATING PLANELB1eEBB2A1(4 PLACES)CeB0º ~ 15º REFSYMBOLAA1DEE1BCOMMON DIMENSIONS(Unit of Measure = mm)MIN–0.50834.5447.620 7.1120.3811.1430.7623.1750.203–NOM––MAX4.5724–NOTE– 34.798 Note 1–––––––– 8.255 7.4930.5331.3971.1433.4290.35610.160Note 1 Note:1.Dimensions D and E1 do not include mold Flash or Protrusion.Mold Flash or Protrusion shall not exceed 0.25 mm (0.010\"). B1B2LCeB e 2.540 TYP09/28/01 2325 Orchard Parkway San Jose, CA 95131TITLE28P3, 28-lead (0.300\"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO.28P3REV. BR9

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32M1-A

DD11230Pin 1 IDE1ESIDE VIEWTOP VIEWA2A3A1KPD2 A0.08CCOMMON DIMENSIONS(Unit of Measure = mm)MIN0.80 – – 0.18 4.90 4.702.954.904.702.95 0.30 – – 0.20–NOM0.90 0.02 0.65 0.20 REF0.235.004.753.105.004.753.100.50 BSC0.40 – – 0.500.6012o –0.305.104.803.255.104.803.25MAX1.000.051.00NOTESYMBOL A A1 A2 A3 E2 b PPin #1 Notch(0.20 R)123K D D1 D2 beEL E1 E2 e L P 0BOTTOM VIEWNote: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. K5/25/06 2325 Orchard Parkway San Jose, CA 95131TITLE32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, 3.10 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO.32M1-AREV. ER10

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Errata

All revisions

No known errata.

1062FS–AVR–07/06

ATtiny28L/V

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Datasheet Revision History

Rev – 01/06GRev – 01/06G

Please note that the referring page numbers in this section are referred to this docu-ment. The referring revision in this section are referring to the document revision.1.Updated chapter layout.

2.Updated “Ordering Information” on page 7.1.Updated description for “Port A” on page 25.2.Added note 6 in “DC Characteristics” on page 54.3.Updated “Ordering Information” on page 7.4.Added “Errata” on page 11.

Rev – 03/05F

1.Updated “Electrical Characteristics” on page 54.

2.MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead Frame Package

QFN/MLF”.3.Updated “Ordering Information” on page 7.

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