MEMORY存储芯片MT48LC4M16A2P-7EIT G中文规格书

1Gb: x16, x32 Automotive Mobile LPDDR2 SDRAM

Functional Description

Functional Description

Mobile LPDDR2 is a high-speed SDRAM internally configured as a 4- or 8-bank memorydevice. LPDDR2 devices use a double data rate architecture on the command/address(CA) bus to reduce the number of input pins in the system. The 10-bit CA bus is used totransmit command, address, and bank information. Each command uses one clock cy-cle, during which command information is transferred on both the rising and fallingedges of the clock.

LPDDR2-S4 devices use a double data rate architecture on the DQ pins to achieve high-speed operation. The double data rate architecture is essentially a 4n prefetch architec-ture with an interface designed to transfer two data bits per DQ every clock cycle at theI/O pins. A single read or write access for the LPDDR2-S4 effectively consists of a single4n-bit-wide, one-clock-cycle data transfer at the internal SDRAM core and four corre-sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

Read and write accesses are burst oriented; accesses start at a selected location andcontinue for a programmed number of locations in a programmed sequence.

Accesses begin with the registration of an ACTIVATE command followed by a READ orWRITE command. The address and BA bits registered coincident with the ACTIVATEcommand are used to select the row and bank to be accessed. The address bits regis-tered coincident with the READ or WRITE command are used to select the bank and thestarting column location for the burst access.

Figure 8: Functional Block Diagram

CKECKCK#CS#CA0CA1CA2CA3CA4CA5CA6CA7CA8CA9ControllogicCommand / AddressMultiplex and DecodeBank 7Bank 7Bank 6Bank 6Bank 5Bank 5Bank 4Bank 4Bank 3Bank 3Bank 2Bank 2Bank 1Bank 1Bank 0Bank 0row-Memory arrayaddresslatchanddecoderCOL0n4nReadlatchnnnMUXnDATADQSgenerator4nDRVRSDQ0–DQn-1xRefreshxcounterRow-addressMUXModeregistersSense amplifierDQS, DQS#Inputregisters44444nnnnDMn4RCVRSDQS, DQS#33BankcontrollogicI/O gatingDM mask logic48WRITE4FIFOMask4and4ndriversnCK, CK#CK outCK in4nDatannnCOL0Column-y - 1address1counter/latchColumndecoderPreliminary

1Gb: x16, x32 Automotive Mobile LPDDR2 SDRAM

Mode Register Definition

Table 30: MR8 Op-Code Bit Definitions (Continued)

FeatureDensityTypeRead-onlyOPOP[5:2]Definition0000b: 64Mb0001b: 128Mb0010b: 256Mb0011b: 512Mb0100b: 1Gb0101b: 2Gb0110b: 4Gb0111b: 8Gb1000b: 16Gb1001b: 32GbAll others: ReservedI/O widthRead-onlyOP[7:6]00b: x3201b: x1610b: x811b: not usedTable 31: MR9 Test Mode (MA[7:0] = 09h)

OP7OP6OP5OP4OP3OP2OP1OP0Vendor-specific test modeTable 32: MR10 Calibration (MA[7:0] = 0Ah)

OP7S4OP6OP5OP4OP3OP2OP1OP0Calibration codeTable 33: MR10 Op-Code Bit Definitions

Notes 1–4 apply to all parameters and conditionsFeatureTypeOPDefinitionCalibration codeWrite-onlyOP[7:0]0xFF: Calibration command after initialization0xAB: Long calibration0x56: Short calibration0xC3: ZQRESETAll others: ReservedNotes:

1.2.3.4.

Host processor must not write MR10 with reserved values.

The device ignores calibration commands when a reserved value is written into MR10.See AC timing table for the calibration latency.

If ZQ is connected to VSSCA through RZQ, either the ZQ calibration function (see MRW ZQCalibration Commands (page 73)) or default calibration (through the ZQRESET com-mand) is supported. If ZQ is connected to VDDCA, the device operates with default cali-