ProfiBus控制器SPC3手册

2021-03-09 来源：爱问旅游网

SIMATIC NET

SPC3 Siemens PROFIBUS Controller

Hardware Description

Date 12/23/99

SIMATIC - NETSPC3Hardware Description(Siemens PROFIBUS Controller according to EN 50170 Vol. 2)Version: 1.1Date: 12/99PROFIBUS Interface CenterSPC3

Liability Exclusion

We have tested the contents of this document regarding agreement withthe hardware and software described. Nevertheless, there may bedeviations, and we don’t guarantee complete agreement. The data in thedocument is tested periodically, however. Required corrections areincluded in subsequent versions. We gratefully accept suggestions forimprovement

Unless permission has been expressly granted, passing on this documentor copying it, or using and sharing its content are not allowed. Offenderswill be held liable. All rights reserved, in the event a patent is granted or autility model or design is registered.

Subject to technical changes.

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SPC3PROFIBUS Interface Center

VersionsReleaseV 1.1

Date12/23/99

Changes

Chapter 8.2 Current consumption without bus accessesChapter 10.1 Contact persons

SPC3 Hardware Description

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PROFIBUS Interface CenterTable of Contents

1234

INTRODUCTIONFUNCTION OVERVIEWPIN DESCRIPTIONMEMORY ALLOCATION

4.14.24.3

Memory Area Distribution in the SPC3Processor Parameters (Latches/Register)Organizational Parameters (RAM)

SPC3

78911

111315

5ASIC INTERFACE

5.1Mode Register5.1.1Mode Register 05.1.2Mode Register 1 (Mode-REG1, writable):5.25.3

Status RegisterInterrupt Controller

1618192124242424

5.4Watchdog Timer5.4.1Automatic Baud Rate Identification5.4.2Baud Rate Monitoring5.4.3Response Time Monitoring

6PROFIBUS-DP INTERFACE

6.1

DP_Buffer Structure

2528

282930313234353535

6.2Description of the DP Services6.2.1Set_Slave_Address (SAP55)6.2.2Set_Param (SAP61)6.2.3Check_Config (SAP62)6.2.4Slave_Diagnosis (SAP60)6.2.5Write_Read_Data / Data_Exchange (Default_SAP)6.2.6Global_Control (SAP58)6.2.7Read_Inputs (SAP56)6.2.8Read_Outputs (SAP57)6.2.9Get_Config (SAP59)

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HARDWARE INTERFACE

7.1Universal Processor Bus Interface7.1.1General Description7.1.2Bus Interface Unit (BIU)7.1.3Switching Diagram Principles7.1.4Application with the 80 C 327.1.5Application with th 80 C 1657.1.6Interface Signals7.27.3

UARTASIC Test

PROFIBUS Interface Center

3636384041424242

8TECHNICAL DATA

8.18.28.38.48.5

Maximum Limit ValuesTypical Values

Permitted Operating ValuesRatings for the Output DriversDC Specification for the I/O Drivers

4343434344454546485052545556

8.6Timing Characteristics8.6.1SYS Bus Interface8.6.2Timing in the Synchronous C32-Mode:8.6.3Timing in the Asynchronous Intel Mode (X86 Mode) :8.6.4Timing in the Synchronous Motorola Mode (E_Clock-Mode, for example, 68HC11) :8.6.5Timing in the Asynchronous Motorola-Mode (for example, 68HC16) :8.6.6Serial Bus Interface8.6.7Housing8.6.8Processing Instructions

9PROFIBUS INTERFACE

9.19.2

Pin Assignment

Example for the RS 485 Interface

5758

10.110.210.3

APPENDIX

Addresses

General Definition of TermsOrdering of ASICs

596060

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11.1

SPC3

616161616363

APPENDIX A: DIAGNOSTICS PROCESSING IN PROFIBUS DP

Introduction

11.2Diagnostics Bits and Expanded Diagnostics11.2.1STAT_DIAG11.2.2EXT_DIAG

11.2.3EXT_DIAG_OVERFLOW11.3

Diagnostics Processing from the System View

12.1

APPENDIX B: USEFUL INFORMATION

Data format in the Siemens PLC SIMATIC

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1 IntroductionPROFIBUS Interface Center

For simple and fast digital exchange between programmable logic controllers, Siemens offers its usersseveral ASICs. These ASICs are based on and are completely handled on the principles of the EN 50170Vol. 2, of data traffic between individual programmable logic controller stations.

The following ASICs are available to support intelligent slave solutions, that is, implementations with amicroprocessor.

The ASPC2 already has integrated many parts of Layer 2, but the ASPC2 also requires a processor’ssupport. This ASIC supports baud rates up to 12 Mbaud. In its complexity, this ASIC is conceived primarilyfor master applications.

Due to the integration of the complete PROFIBUS-DP protocol, the SPC3 decisively relieves the processor ofan intelligent PROFIBUS slave. The SPC3 can be operated on the bus with a baud rate of up to 12 MBaud.However, there are also simple devices in the automation engineering area, such as switches andthermoelements, that do not require a microprocessor to record their states.

There are two additional ASICs available with the designations SPM2 (Siemens Profibus Multiplexer, Version2 ) and LSPM2 (Lean Siemens PROFIBUS Multiplexer) for an economical adaptation of these devices.These blocks work as a DP slave in the bus system (according to DIN E 19245 T3) and work with baud ratesup to 12 Mbaud. A master addresses these blocks by means of Layer 2 of the 7 layer model. After theseblocks have received an error-free telegram, they independently generate the required response telegrams.The LSPM2 has the same functions as the SPM2, but the LSPM2 has a decreased number of I/O ports anddiagnostics ports.

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PROFIBUS Interface Center2 Function OverviewSPC3

The SPC3 makes it possible to have a price-optimized configuration of intelligent PROFIBUS-DP slaveapplications.

The processor interface supports the following processors:

Intel:

Siemens:Motorola:

80C31, 80X8680C166/165/167

HC11-,HC16-,HC916 types

In SPC3, the transfer technology is integrated (Layer 1), except for analog functions (RS485 drivers), the FDLtransfer protocol (Fieldbus Data Link) for slave nodes (Layer 2a), a support of the interface utilities (Layer 2b),some Layer 2 FMA utilities, and the complete DP slave protocol (USIF: User Interface, which makes itpossible for the user to have access to Layer 2). The remaining functions of Layer 2 (software utilities andmanagement) must be handled via software.

The integrated 1.5k Dual-Port-RAM serves as an interface between the SPC3 and the software/application.The entire memory is subdivided into 192 segments, with 8 bytes each. Addressing from the user takesplace directly and from the internal microsequencer (MS) by means of the so-alled base pointer. The base-pointer can be positioned at any segment in the memory. Therefore, all buffers must always be located at thebeginning of a segment.

If the SPC3 carries out a DP communication the SPC3 automatically sets up all DP-SAPs. The varioustelegram information is made available to the user in separate data buffers (for example, parameter settingdata and configuration data). Three change buffers are provided for data communication, both for the outputdata and for the input data. A change buffer is always available for communication. Therefore, no resourceproblems can occur. For optimal diagnostics support, SPC3 has two diagnostics change buffers into whichthe user inputs the updated diagnostics data. One diagnostics buffer is always assigned to SPC3 in thisprocess.

The bus interface is a parameterizable synchronous/asynchronous 8-bit interface for various Intel andMotorola microcontrollers/processors. The user can directly access the internal 1.5k RAM or the parameterlatches via the 11-bit address bus.

After the processor has been switched on, procedural-specific parameters (station address, control bits, etc.)must be transferred to the Parameter Register File and to the mode registers.The MAC status can be scanned at any time in the status register.

Various events (various indications, error events, etc.) are entered in the interrupt controller. These eventscan be individually enabled via a mask register. Acknowledgement takes place by means of theacknowledge register. The SPC3 has a common interrupt output.

The integrated Watchdog Timer is operated in three different states: ‘Baud_Search’, ‘Baud_Control,’ and‘DP_Control’.

The Micro Sequencer (MS) controls the entire process.

Procedure-specific parameters (buffer pointer, buffer lengths, station address, etc.) and the data buffer arecontained in the integrated 1.5kByte RAM that a controller operates as Dual-Port-RAM.

In UART, the parallel data flow is converted into the serial data flow, or vice-versa. The SPC3 is capable ofautomatically identifying the baud rates (9.6 kBd - 12 MBd).

波特率自适应The Idle Timer directly controls the bus times on the serial bus cable.

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3 Pin DescriptionThe SPC3 has a 44-pin PQFP housing with the following signals:

Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23Signal NameXCSXWR/E_ClockDIVIDERXRD/R_WCLKVSSCLKOUT2/4XINT/MOTX/INTAB10DB0DB1XDATAEXCHXREADY/XDTACKDB2DB3VSSVDDDB4DB5DB6DB7MODEIn/OutI©I©I©I©I(TS)OI©OI(CPD)I©/OI©/OOOI©/OI©/ODescriptionChip-SelectPROFIBUS Interface Center

Source / DestinationCPU (80C165)CPUC32 Mode: place on VDD.C165 Mode: CS-SignalWrite signal /EI_Clock for MotorolaSetting the scaler factor for CLK2OUT2/4.low potential means divided through 4Read signal / Read_Write for MotorolaClock pulse inputClock pulse divided by 2 or 4 0 = Intel interface 1 = Motorola interfaceInterruptAddress busCPUSystemSystem, CPUSystemCPU, Interrupt-Contr.C32 mode: 0C165 mode: address busData busC32 Mode: Data/address busmultiplexedC165 Mode: Data/address busseparatedData_Exchange state for PROFIBUS-DPReady for external CPUData busC32 mode: data bus/addressbus multiplexedC165 mode: data/address busseparateCPU, memoryLEDSystem, CPUCPU, memoryI©/OI©/OI©/OI©/OIData busC32 mode: data bus/addressbus multiplexedC165 mode: data bus/addressCPU, memorybus separate 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44ALE/ASAB9TXDRTSVSSAB8RXDAB7AB6XCTSXTEST0XTEST1RESETAB4VSSVDDAB3AB2AB5AB1AB0I©IOOI©I©I©I©I©I©I©I(CS)I© 0 = 80C166 Data bus/address bus separated; readysignal 1 = 80C32 data bus/address bus multiplexed, fixedtimingAddress latchC32 mode: ALEenableC165 mode: 0Address busC32 mode: 0C165 mode: address busSerial send portRequest to SendAddress busC32 Mode : 0C165 Mode: address busSystemCPU (80C32)CPU (C165), memoryRS 485 senderRS 485 senderSerial receive portAddress busAddress busClear to send 0 = send enablePin must be placed fixed at VDD.Pin must be placed fixed at VDD.Connect reset input with CPU’s port pin.Address busRS 485 receiverSystem, CPUSystem, CPUFSK modemSystem, CPUI©I©I©I©I©Address busAddress busSystem, CPUSystem, CPUFigure 3.1: SPC3 Pin Assignment

Note: • All signals that begin with X.. are LOW active

• VDD = +5V, VSS = GNDSPC3 Hardware Description

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PROFIBUS Interface Center

Input levels:

I ©:I (CS):I (CPD):I (TS):

SPC3

CMOS

CMOS Schmitt triggerCMOS with pull downTTLt Schmitt trigger

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4 Memory Allocation4.1 Memory Area Distribution in the SPC3

PROFIBUS Interface Center

The figure displays the division of the SPC3 1.5k internal address area.

The internal latches/register are located in the first 21 addresses. The internal latches/register either comefrom the controller or influence the controller. Certain cells can be only read or written. The internal workcells to which the user has no access are located in RAM at the same addresses.

The organizational parameters are located in RAM beginning with address 16H. The entire buffer structure(for the DP-SAPS) is written based on these parameters. In addition, general parameter setting data (stationaddress, Ident no., etc.) are transferred in these cells and the status displays are stored in these cells (globalcontrol command, etc.).

Corresponding to the parameter setting of the organizational parameters, the user-generated buffers arelocated beginning with address 40H. All buffers or lists must begin at segment addresses (48 bytessegmentation).Address000H016H040H

Function

Processor parametersinternal work cellsLatches/register(22 bytes)

Organizationalparameters(42 bytes)DP- buffer:Data In (3) *输入数据是指SPC3发出给主机的丆in/out都是站在主机的角度Data Out (3) *Diagnostics (2)

Parameter setting data (1)Configuration data (2)Auxiliary buffer (2)SSA-buffer(1)

5FFH

Figure 4.1: SPC3 Memory Area Distribution

Caution:

The HW prohibits overranging the address area. That is, if a user writes or reads past the memoryend, 400H is subtracted from this address and the user therefore accesses a new address. Thisprohibits overwriting a process parameter. In this case, the SPC3 generates the RAM accessviolation interrupt. If the MS overranges the memory end due to a faulty buffer initialization, the sameprocedure is executed.

* Data In is the input data from PROFIBUS slave to master Data out is the output data from PROFIBUS master to slave

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PROFIBUS Interface CenterSPC3

The complete internal RAM of the SPC 3 is divided logically into 192 segments. Each segment consists of 8bytes. For more informations about the contents of the 3 memory areas see previous chapter.The physicaladdress is build by multiplikation with 8.

internal SPC 3 RAM (1.5 kByte)Segment 0Segment 1Segment 28 Bit Segmentaddresses(Pointer to the buffers70+100Segment 190Segment 191Page 12

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4.2 Processor Parameters (Latches/Register)

PROFIBUS Interface Center

These cells can be either read only or written only. SPC3 carries out “address swapping” for an access to theaddress area 00H - 07H (word register) in the Motorola mode. That is, the SPC3 exchangesaddress bit 0 (generated from an even address, one uneven, and vice-versa). The following sections moreclearly explain the significance of the individual registers. AddressIntel / Motorla00H01H01H00H02H03H03H02H04H05H05H04H06H07H07H06H08H09H0AH0BH0CH0DH0EH0FH10H11H12H13H14H15HSPC3自己完成Motorola模式下的地址不兼容问题丆无需我费心。Name Bit No.Significance (Read Access!)Int-Req-Reg 7..0Interrupt Controller RegisterInt-Req-Reg 15..8Int—Reg 7..0Int—Reg 15..8Status-Reg 7..0Status RegisterStatus-Reg 15..8ReservedDIN_Buffer_SM 7..0Buffer assignment of theDP_Din_Buffer_State_MachineNew_DIN_Buffer_Cmd 1..0The user makes a new DP Din buffer available in theN state.DOUT_Buffer_SM 7..0Buffer assignment of theDP_Dout_Puffer_State_MachineNext_DOUT_Buffer_Cmd 1..0The user fetches the last DP Dout-Buffer from the Nstate.DIAG_Buffer_SM 3..0Buffer assignment for theDP_Diag_Puffer_State_MachineNew_DIAG_Puffer_Cmd 1..0The user makes a new DP Diag Buffer available tothe SPC3.User_Prm_Data_OK 1..0The user positively acknowledges the userparameter setting data of a Set_Param-Telegram.UserPrmDataNOK 1..0The user negatively acknowledges the userparameter setting data of a Set_Param-Telegram.User_Cfg_Data_OK 1..0The user positively acknowledges the configurationdata of a Check_Config-Telegram.User_Cfg_Data_NOK 1..0The user negatively acknowledges the configurationdata of a Check_Config-Telegram.ReservedSSA_BufferfreecmdReservedThe user has fetched the data from the SSA bufferand enables the buffer again.Figure 4.2: Assignment of the Internal Parameter Latches for READ

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AddressIntel/Motorola00H01H01H00H02H03H03H02H04H05H05H04H06H07H07H06H08H09H0AH0BHOCH0DH0EH0FH10H11H12H13H14H15HSPC3

Name Bit No.Significance (Write Access !)Int-Req-Reg 7..0Interrupt- Controller - RegisterInt-Req_Reg 15..8Int-Ack-Reg 7..0Int-Ack-Reg 15..8Int—Mask-Reg 7..0Int—Mask-Reg 15..8Mode-Reg0 7..0Setting parameters for individual bitsMode-Reg0-S 15..8Mode-Reg1-S 7..0Mode-Reg1-R 7..0WD Baud Ctrl -Val 7..0Root value for baud rate monitoringMinTsdr_Val 7..0ReservedMinTsdr timeFigure 4.3: Assignment of the Internal Parameter Latches for WRITE

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4.3 Organizational Parameters (RAM)

PROFIBUS Interface Center

The user stores the organizational parameters in RAM under the specified addresses. These parameterscan be written and read.AddressIntel/Motorola16H17H18H19H19H18H1AH1BH1CH1DH1EH1FH20H21H22H23H24H25H26H27H28H29H2AH2BH2CH2DH2EH2FH30H31H32H33H34H35H36H37H38H39H3AH3BH3CH3DHName Bit No.SignificanceR_TS_Adr 7..0Set up station address of the relevant SPC3reservedPointer to a RAM address which is presetted with 0FFHR_User_Wd_Value 7..0Based on an internal 16-bit wachdog timer, the user ismonitored in the DP_Mode.R_User_Wd_Value 15 ..8R_Len_Dout_PufLength of the 3 Dout buffersR_Dout_buf_Ptr1Segment base address of Dout buffer 1二级跳转的意思。R_Dout_buf_Ptr2Segment base address of Dout buffer 2每8字节为一组丆共192组R_Dout_buf_Ptr3Segment base address of Dout buffer 3R_Len_Din_bufLength of the 3 Din buffersR_Din_buf_Ptr1Segment base address of Din buffer 1R_Din_buf_Ptr2Segment base address of Din buffer 2R_Din_buf_Ptr3Segment base address of Din buffer 3reservedPreset with 00H.reservedPreset with 00H.R Len Diag buf1Length of Diag buffer 1R Len Diag buf2Length of Diag buffer 2R_Diag_Puf_Ptr1Segment base address of Diag buffer 1R_Diag_Puf_Ptr2Segment base address of Diag buffer 2R Len Cntrl Pbuf1Length of Aux buffer 1 and the control buffer belonging to it,for example, SSA-Buf, Prm-Buf, Cfg-Buf, Read-Cfg-BufR Len Cntrl Puf2Length of Aux-Buffer 2 and the control buffer belonging to it,for example, SSA-Buf, Prm-Buf, Cfg-Buf, Read-Cfg-BufR Aux Puf SelBit array, in which the assignments of the Aux-buffers ½ aredefined to the control buffers, SSA-Buf, Prm-Buf, Cfg-BufR_Aux_buf_Ptr1Segment base address of auxiliary buffer 1R_Aux_buf_Ptr2Segment base address of auxiliary buffer 2R_Len_SSA_DataLength of the input data in the Set_Slave_Address-bufferR SSA buf PtrSegment base address of the Set_Slave_Address-bufferR_Len_Prm_DataLength of the input data in the Set_Param-bufferR_Prm_buf_PtrSegment base address of the Set_Param-bufferR_Len_Cfg_DataLength of the input data in the Check_Config-bufferR Cfg Buf PtrSegment base address of the Check_Config-bufferR_Len_Read_Cfg_DataLength of the input data in the Get_Config-bufferR_Read_Cfg_buf_PtrSegment base address of the Get_Config-bufferreservedPreset with 00H.reservedPreset with 00HreservedPreset with 00H.reservedPreset with 00H.R_Real_No_Add_ChangeThis parameter specifies whether the DP slave address mayagain be changed at a later time point.R_Ident_LowThe user sets the parameters for the Ident_Low value.R_Ident_HighThe user sets the parameters for the Ident_High value.R_GC_CommandThe Global_Control_Command last receivedR_Len_Spec_Prm_bufIf parameters are set for the Spec_Prm_Buffer_Mode (seemode register 0), this cell defines the length of the parambuffer.Figure 4.4: Assignment of the Organizational ParametersSPC3 Hardware Description

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PROFIBUS Interface Center5 ASIC InterfaceSPC3

The registers that determine both the hardware function of the ASIC as well as telegram processing aredescribed in the following.

5.1 Mode Register

Parameter bits that access the controller directly or which the controller directly sets are combined in twomode registers (0 and 1) in the SPC3.5.1.1 Mode Register 0

Setting parameters for Mode Register 0 takes place in the offline state only (for example, after switchingon). The SPC3 may not exit offline until Mode Register 0, all processor parameters, and organizationalparameters are loaded (START_SPC3 = 1, Mode-Register 1).AddressControlRegister06H(Intel)

Freeze_Support-ed

Sync_Support-ed

EARLY_RDY

Bit Position43

INT_POL

MinTSDR

Designation

DIS_STOP_CONTROL

DIS_START_CONTROL

Mode Reg07..0

AddressControlRegister07H(Intel)

151413

Bit Position1211

Test

Designation

UserTimebase

EOITimebase

DPMode

Spec_CleSpec_Prm_ar_ModePuf_Mode

*)**)

Mode-Reg0

13 .. 8

*) When Spec_Clear_Mode (Fail Safe Mode ) = 1 the SPC3 will accept data telegramm with a data unit=0 inthe state Data Exchange. The reaction to the outputs can be parameterized f.e. in the parameterizationtelegram ( only available from version Step C).

**) When using a big number of parameters to be transmitted from the PROFIBUS-Master to the slave theAuxiliary buffer ½ has to have the same size like the Parameterization buffer. Sometimes this could reach thelimit of the available memory space in the SPC3. When Spec_Prm_Puf_Mode = 1 the parameterization dataare processed directly in this special buffer and the Auxiliary buffers can be held compact.

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Bit 0

PROFIBUS Interface Center

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

Bit 9

Bit 10

Bit 11

Bit 12

Bit 13

DIS_START_CONTROL

Monitoring the following start bit in UART. Set-Param Telegram overwrites this memory cell inthe DP mode. (Refer to the user-specific data.)

0 =Monitoring the following start bit is enabled.1 =Monitoring the following start bit is switched off.

DIS_STOP_CONTROL

Stop bit monitoring in UART. Set-Param telegram overwrites this memory cell in the DP mode.(Refer to the user-specific data.)

0 =Stop bit monitoring is enabled.1 =Stop bit monitoring is switched off.

EN_FDL_DDB

Reserved

0 =The FDL_DDB receive is disabled.

MinTSDR

Default setting for the MinTSDR after reset for DP operation or combi operation

0 =Pure DP operation (default configuration!)1 =Combi operation

INT_POL

Polarity of the interrupt output

0 =The interrupt output is low-active.1 =The interrupt output is high-active.

EARLY_RDY

Moved up ready signal

0 =Ready is generated when the data are valid (read) or when the data are accepted

(write).

1 =Ready is moved up by one clock pulse.

Sync_Supported

Sync_Mode support

0 =Sync_Mode is not supported.1 =Sync_Mode is supported.

Freeze_Supported

Freeze_Mode support

0 =Freeze_Mode is not supported.1 =Freeze_Mode is supported.

DP_MODE

DP_Mode enable

0 =DP_Mode is disabled.1 =DP_Mode is enabled. SPC3 sets up all DP_SAPs.

EOI_Time base

Time base for the end of interrupt pulse

0 =The interrupt inactive time is at least 1 usec long.1 =The interrupt inactive time is at least 1 ms long.

User_Time base

Time base for the cyclical User_Time_Clock-Interrupt

0 =The User_Time_Clock-Interrupt occurs every 1 ms.1 =The User_Time_Clock-Interrupt occurs every 10 ms.

WD_Test

Test mode for the Watchdog-Timer, no function mode

0 =The WD runs in the function mode.1 =Not permitted

Spec_Prm_Puf_Mode

Special parameter buffer

0 =No special parameter buffer.1 =Special parameter buffer mode .Parameterization data will be stored directly in the

special parameter buffer.

Spec_Clear_Mode

Special Clear Mode (Fail Safe Mode)

0 =1 =No special clear mode.

Special clear mode. SPC3 will accept datea telegramms with data unit = 0.

Figure 5.1: Mode-Register 0 Bit 12 .. 0.(can be written to, can be changed in offline only)

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5.1.2 Mode Register 1 (Mode-REG1, writable):

SPC3

Some control bits must be changed during operation. These control bits are combined in Mode-Register 1and can be set independently of each other (Mode_Reg_S) or can be deleted independently of each other(Mode_Reg_R). Various addresses are used for setting and deleting. Log ‘1’ must be written to the bitposition to be set or deleted.AddressControlRegister08H

Bit Position43

User_

Leave_MasterUser_Leave_Master

Designation

Go_OfflineGo_Offline

EOI

START_SPC3START_SPC3

09H

Res_EN_User_WDChange_

Cfg_Puffer

Res_EN_User_WDChange_

Cfg_Puffer

Mode-Reg_S7..0

Mode-Reg_R7..0

EOI

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

START_SPC3

Exiting the Offline state1 =SPC3 exits offline and goes to passive-idle. In addition, the idle timer and

Wd timer are started and ‘Go_Offline = 0’ is set.

EOI

End of Interrupt

1 =End of Interrupt: SPC3 switches the interrupt outputs to inactive and again

sets EOI to log.’0.’

Go_Offline

Going into the offline state

1 =After the current requests ends, SPC3 goes to the offline state and again

sets Go_Offline to log.’0.’

User_Leave_Master

Request to the DP_SM to go to ‘Wait_Prm.’

1 =The user causes the DP_SM to go to ‘Wait_Prm.’ After this action, SPC3

sets User_Leave_Master to log.’0.’

En_Change_Cfg_Puffer

Enabling buffer exchange (Cfg buffer for Read_Cfg buffer)

0 =With ‘User_Cfg_Data_Okay_Cmd,’ the Cfg buffer may not be exchanged for

the Read_Cfg buffer.

1 =With ‘User_Cfg_Data_Okay_Cmd,’ the Cfg buffer must be exchanged for the

Read_Cfg buffer.

Res_User_Wd

Resetting the User_WD_Timers

1 =SPC3 again sets the User_Wd_Timer to the parameterized value

‘User_Wd_Value15..0.’ After this action, SPC3 sets Res_User_Wd to log.’0.’

Figure 5..2: Mode Register1 S and Mode Register1 R Bit7..0.(writable)

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5.2 Status Register

PROFIBUS Interface Center

The status register mirrors the current SPC3 status and can be read only.AddressControlRegister04H(Intel)

Bit Position43

RAM

accessviolation

Designation

Diag_Flag

FDL_IND_ST

Offline/Passive-Idle

WD_State1

DP_State1

Status-Reg7..0

AddressControlRegister05H(Intel)

151413

Bit Position1211

Designation

Status-Reg

15 .. 80

SPC3 Release

Baud Rate2

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Bit 0

SPC3

Bit 1

Bit 2

Bit 3

Bits4,5

Offline/Passive-Idle

Offline-/Passive-Idle state

0 =SPC3 is in offline.

1 =SPC3 is in passive idle.

FDL_IND_ST

FDL indication is temporarily buffered.

0 =No FDL indication is temporarily buffered.1 =No FDL indication is temporarily buffered.

Diag_Flag

Status diagnostics buffer

0 =The DP master fetches the diagnostics buffer.

1 =The DP master has not yet fetched the diagnostics buffer.

RAM Access Violation

Memory access > 1.5kByte

0 =No address violation

1 =For addresses > 1536 bytes, 1024 is subtracted from the current address,

and there is access to this new address.

DP-State1..0

DP-State Machine state

00 =’Wait_Prm’ state01=’Wait_Cfg’ state10 =’DATA_EX’ state11=Not possible

WD-State1..0

Watchdog-State-Machine state

00 =’Baud_Search’ state01=’Baud_Control’ state10 =’DP_Control’ state11=Not possible

Baud rate3..0:

The baud rates SPC3 found

0000 =12 MBaud0001 =6 MBaud0010 =3 MBaud0011 =1.5 MBaud0100 =500 kBaud0101 =187.5 kBaud0110 =93.75 kBaud0111 =45.45 kBaud1000 =19.2 kBaud1001 =9.6 kBaudRest =Not possible

SPC3-Release3..0:

Release no. for SPC3

0000 =Release 0Rest =Not possible

Bits6,7

Bits8,910,11

Bit 1213,14,15

Figure 5.3: Status Register Bit15 .. 0.(readable)

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SPC3

5.3 Interrupt Controller

PROFIBUS Interface Center

The processor is informed about indication messages and various error events via the interrupt controller. Upto a total of 16 events are stored in the interrupt controller. The events are carried out on an interrupt output.The controller does not have a prioritization level and does not provide an interrupt vector (not 8259Acompatible!).

The controller consists of an Interrupt Request Register (IRR), an Interrupt Mask Register (IMR), an InterruptRegister (IR), and an Interrupt Acknowledge Register (IAR).

uPSPC3uPuPuPSEP_INTIR4个中断寄存器丗IRR:IMR:IR:IAR:SIRRRSIMRRFFX/INTuPINT_PolIARuPEach event is stored in the IRR. Individual events can be suppressed via the IMR. The input in the IRR isindependent of the interrupt masks. Event signals not masked out in the IMR generate the X/INT interrupt viaa sum network. The user can set each event in the IRR for debugging.

Each interrupt event the processor processed must be deleted via the IAR (except for New_Prm_Data,New_DDB_Prm_Data, and New_Cfg_Data). Log ‘1’ must be written on the relevant bit position. If a newevent and an acknowledge from the previous event are present at the IRR at the same time, the eventremains stored. If the processor subsequently enables a mask, it must be ensured that no prior input ispresent in the IRR. For safety purposes, the position in the IRR must be deleted prior to the mask enable.Prior to exiting the interrupt routine, the processor must set the “end of interrupt signal (E01) = 1” in the moderegister. The interrupt cable is switched to inactive with this edge change. If another event must be stored,the interrupt output is not activated again until after an interrupt inactive time of at least 1 usec or 1-2 ms.This interrupt inactive time can be set via ‘EOI_Timebase.’ This makes it possible to again come into theinterrupt routine when an edge-triggered interrupt input is used.

The polarity for the interrupt output is parameterized via the INT_Pol mode bit. After the hardware reset, theoutput is low-active.AddressControlRegister00H(Intel)AddressControlRegister01H(Intel)

Bit Position43

User_Timer_Clock

WD_DP_Mode_Timeout

Designation

Baud_rate_Detect

Res

Go/LeaveData_EX

MAC_Reset

Int-Req-Reg7..0Designation

Res

DX_OUT

Bit Position1211

Diag_Puffer_Changed

New_Prm_Data

New_Cfg_Data

New_SSA_Data

New_GCCommand

Int-Req-Reg 715..8

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Bit 0

SPC3

Bit 1Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7Bit 8

Bit 9

Bit 10

Bit 11

Bit 12

Bit 13

Bit 14Bit 15

MAC_Reset

After it processes the current request, the SPC3 has arrived at the offline state (throughsetting the ‘Go_Offline bit’ or through a RAM access violation).Go/Leave_DATA_EX

The DP_SM has entered or exited the ‘DATA_EX’ state.Baudrate_Detect

The SPC3 has exited the ‘Baud_Search state’ and found a baud rate.WD_DP_Control_Timeout

The watchdog timer has run out in the ‘DP_Control’ WD state.User_Timer_Clock

The time base for the User_Timer_Clocks has run out (1/10ms).Res

For additional functionsRes

For additional functionsNew_GC_Command

The SPC3 has received a ‘Global_Control telegram’ with a changed ‘GC_Command-Byte,’ and this byte is stored in the ‘R_GC_Command’ RAM cell.New_SSA_Data

The SPC3 has received a ‘Set_Slave_Address telegram’ and made the data available inthe SSA buffer.New_Cfg_Data

The SPC3 has received a ‘Check_Cfg telegram’ and made the data available in the Cfgbuffer.

New_Prm_Data

The SPC3 has received a ‘Set_Param telegram’ and made the data available in the Prmbuffer.

Diag_Puffer_Changed

Due to the request made by ‘New_Diag_Cmd,’ SPC3 exchanged the diagnostics bufferand again made the old buffer available to the user.DX_OUT

The SPC3 has received a ‘Write_Read_Data telegram’ and made the new output dataavailable in the N buffer. For a ‘Power_On’ or for a ‘Leave_Master,’ the SPC3 deletesthe N buffer and also generates this interrupt.Res

For additional functionsRes

For additional functions

Figure 5.4: Interrupt Request Register, IRR Bit 15..0 (writable and readable)

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SPC3PROFIBUS Interface Center

The other interrupt controller registers are assigned in the bit positions, like the IRR.Address02H /03H04H /05H02H /03HRegisterInterrupt Register(IR)Interrupt MaskRegister(IMR)InterruptAcknowledgeRegister(IAR)Reset StateReadable onlyAll bits deletedWritable, canbe changedduringoperationWritable, canbe changedduringoperationAll bits setAssignmentAll bits deletedBit = 1Mask is set and the interruptis disabled.Bit = 0Mask is deleted and theinterrupt is enabled.Bit = 1The IRR bit is deleted.Bit = 0The IRR bit remainsunchanged.Figure 5.5: Additional Interrupt Registers

The ‘New_Prm_Data’, ‘New_Cfg_Data’ inputs may not be deleted via the Interrupt Acknowledge Register.The relevant state machines delete these inputs through the user acknowledgements (for example,‘User_Prm_Data_Okay’ etc.).

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5.4 Watchdog Timer

5.4.1 Automatic Baud Rate Identification

SPC3

The SPC3 is able to identify the baud rate automatically. The „baud search“ state is located after eachRESET and also after the watchdog (WD) timer has run out in the ‘Baud_Control_state.’

As a rule, SPC3 begins the search for the set rate with the highest baud rate. If no SD1 telegram, SD2telegram, or SD3 telegram was received completely and without errors during the monitoring time, the searchcontinues with the next lowest baud rate.

After identifying the correct baud rate, SPC3 switches to the “Baud_Control” state and monitors the baudrate. The monitoring time can be parameterized (WD_Baud_Control_Val). The watchdog works with a clockof 100 Hz (10 msec). The watchdog resets each telegram received with no errors to its own station address.If the timer runs out, SPC3 again switches to the baud search state.5.4.2 Baud Rate Monitoring

The located baud rate is constantly monitored in ‘Baud_Control.’ The watchdog is reset for each error-freetelegram to its own station address. The monitoring time results from multiplying both‘WD_Baud_Control_Val’ (user sets the parameters) by the time base (10 ms). If the monitoring time runsout, WD_SM again goes to ‘Baud_Search’. If the user carries out the DP protocol (DP_Mode = 1, see Moderegister 0) with SPC3, the watchdog is used for the “DP_Control’ state, after a ‘Set_Param telegram’ wasreceived with an enabled response time monitoring ‘WD_On = 1.’ The watchdog timer remains in the baudrate monitoring state when there is a switched off ‘WD_On = 0’ master monitoring. The PROFIBUS DP statemachine is also not reset when the timer runs out. That is, the slave remains in the DATA_EXchange state,for example.

5.4.3 Response Time Monitoring

The ‘DP_Control’ state serves response time monitoring of the DP master (Master_Add). The set monitoringtimes results from multiplying both watchdog factors and multiplying the result with the momentarily valid timebase (1 ms or 10 ms):

TWD = (1 ms or 10 ms) * WD_Fact_1 * WD_Fact_2 (See byte 7 of the parameter setting telegram.)

The user can load the two watchdog factors (WD_Fact_1, and WD_Fact_2) and the time base thatrepresents a measurement for the monitoring time via the ‘Set_Param telegram’ with any value between 1and 255.

EXCEPTION: The WD_Fact_1=WD_Fact_2=1 setting is not permissible. The circuit does not checkthis setting.

Monitoring times between 2 ms and 650 s - independent of the baud rate - can be implemented with thepermisible watchdog factors.

If the monitoring time runs out, the SPC3 goes again to ‘Baud_Control,’ and the SPC3 generates the‘WD_DP_Control_Timeout-Interrupt’. In addition, the DP_State machine is reset, that is, generates the resetstates of the buffer management.

If another master accepts SPC3, then there is either a switch to ‘Baud_Control” (WD_On = 0), or there is adelay in ‘DP_Control’ (WD_On = 1), depending on the enabled response time monitoring (WD_On = 0).

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6 PROFIBUS-DP Interface6.1 DP_Buffer Structure

PROFIBUS Interface Center

The DP mode is enabled in the SPC3 with ‘DP_Mode = 1’ (see mode Register0). In this process, thefollowing SAPS are fixed reserved for the DP mode:

‘‘‘‘‘‘‘‘‘‘

Default SAP:SAP53:SAP55:SAP56:SAP57:SAP58:SAP59:SAP60:SAP61:SAP62:Data exchange (Write_Read_Data)reserved

Changing the station address (Set_Slave_Address)Reading the inputs (Read_Inputs)Reading the outputs (Read_Outputs)

Control commands to the DP-Slave (Global_Control)Reading configuration data (Get_Config)

Reading diagnostics information (Slave_Diagnosis)Sending parameter setting data (Set_Param)Checking configuration data (Check_Config)

The DP Slave protocol is completely integrated in the SPC3 and is handled independently. The user mustcorrespondingly parameterize the ASIC and process and acknowledge transferred messages. Except for thedefault SAP, SAP56, SAP57, and SAP58, all SAPS are always enabled. The remaining SAPS are notenabled until the the DP Slave Machine (DP_SM) goes into the ‘DATA_EX’ state. The user has thepossibility of disabling SAP55. The relevant buffer pointer R_SSA_Puf_Ptr must be set to ‘00H’ for thispurpose. The DDB utility is disabled by the already described initialization of the RAM cells.

The DP_SAP buffer structure is displayed in Figure 6.1. The user configures all buffers (length and bufferbeginning) in the ‘offline state.’ During operation, the buffer configuration must not be changed, except forthe length of the Dout-/Din buffers.

The user may still adapt these buffers in the ‘Wait_Cfg’ state after the configuration telegram (Check_Config).Only the same configuration may be accepted in the ‘DATA_EX’ state.

The buffer structure is divided into the data buffer, diagnostics buffer, and the control buffer.

Both the output data and the input data have three buffers each available with the same length. Thesebuffers function as change buffers. One buffer is assigned to the ‘D’ data transfer, and one buffer is assignedto the ‘U’ user. The third buffer is either in a Next ‘N’ state or Free ‘F’ state, whereby one of the two states isalways unoccupied.

Two diagnostics buffers that can have varying lengths are available for diagnostics. One diagnostics buffer isalways the ‘D’ assigned to SPC3 for sending. The other diagnostics buffer belongs to the user for preparingnew diagnostics data, ‘U.’

The SPC3 first reads the different parameter setting telegrams (Set_Slave_Address, and Set_Param) andthe configuring telegram (Check_Config) into Aux-Puffer1 or Aux-Puffer 2.....

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D-Nis changed by SPC 3DNSPC3

N- U is changed by the userUDout-bufferDNUDin-bufferDUDiagnostics-bufferUARTRead-Config-bufferUserAux1/2-bufferConfig-bufferSSA-bufferAux1/2-bufferParam-bufferFigure 6.1: DP_SAP Buffer Structure

Data exchanged with the corresponding target buffer (SSA buffer, Prm buffer, and Cfg buffer). Each of thebuffers to be exchanged must have the same length. The user defines which Aux_buffers are to be used forthe above-named telegrams in the ‘R_Aux_Puf_Sel’ parameter cell. The Aux- buffer1 must always beavailable. The Aux-buffer2 is optional. If the data profiles of these DP telegrams are very different, such asthe data amount in the Set_Param telegram is significantly larger than for the other telegrams, it is suggestedto make an Aux-Buffer2 available (Aux_Sel_Set_Param = 1) for this telegram. The other telegrams are thenread via Aux-Buffer 1 (Aux_Sel_..=0). If the buffers are too small, SPC3 responds with “no resources”!

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SPC3

AddressRAMRegister2AH

Bit Position4320

Set_

Slave_Adr

Check_Cfg

PROFIBUS Interface Center

Designation0

Set_Prm

R_Aux_Puf_SelSee below for coding.

X101

Coding

Aux_Buffer1Aux_Buffer2

X1X1

Figure 6.2: Aux-Buffer Management

The user makes the configuration data (Get_Config) available in the Read_Cfg buffer for reading. TheRead_Cfg buffer must have the same length as the Cfg_buffer.

The Read_Input_Data telegram is operated from the Din buffer in the ‘D state’, and the Read_Output_Datatelegram is operated from the Dout buffer in the ‘U state.’

All buffer pointers are 8-bit segment addresses, because the SPC3 internally has only 8-bit address registers.For a RAM access, SPC3 adds an 8-bit offset address to the segment address shifted by 3 bits (result: 11-bitphysical address). As regards the buffer start addresses, this results in an 8-byte graunularity from thisspecification.

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6.2 Description of the DP Services

6.2.1 Set_Slave_Address (SAP55)

SPC3

6.2.1.1 Sequence for the Set_Slave_Address UtilityThe user can disable this utility by setting the ‘R_SSA_Puf_Ptr = 00H’ buffer pointer. The slave address mustthen be determined, for example, by reading a switch, and written in the R_TS_Adr. RAM register.

The user must make a retentive memory possibility available (for example, EEPROM) to support this utility. Itmust be possible to store the ‘station address’ and the ‘Real_No_Add_Change’ (‘True’ = FFH) parameter inthis external EEPROM. After each restart caused by a power failure, the user must again make these valuesavailable to SPC3 in the R_TS_Adr und R_Real_No_Add_Change RAM register.

If SAP55 is enabled and the Set_Slave_Address telegram is correctly accepted, SPC3 enters all net data inthe Aux-Puffer1/2, exchanges the Aux buffer1/2 for the SSA buffer, stores the entered data length in‘R_Len_SSA_Data’, generates the ‘New_SSA_Data’ interrupt and internally stores the new ‘station address’and the new ‘Real_No_Add_Change’ parameter. The user does not need to transfer this changed parameterto SPC3 again. After the user has read the buffer, the user generates the ‘SSA_Puffer_Free_Cmd’ (readoperation on address 14H). This makes SPC3 again ready to receive an additional Set Slave Addresstelegram (such as from another master).

SPC3 reacts independently when there are errors.AddressControlRegister14H

Bit Position4300don´t care

Designation

SSA_Puffer_Free_Cmd

Figure 6.3: Coding SSA_Buffer_Free_Cmd

6.2.1.2 Structure of the Set_Slave_Address TelegramThe net data are stored as follows in the SSA buffer:Byte

01234-243

Bit Position43

Designation

New_Slave_Address

Ident_Number_HighIdent_Number_LowNo_Add_Chg

Rem_Slave_Data additional application-specific data

Figure 6.4: Data Format for the Set_Slave_Address Telegram

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SPC3

6.2.2 Set_Param (SAP61)

PROFIBUS Interface Center

6.2.2.1 Parameter Data StructureSPC3 evaluates the first seven data bytes (without user prm data), or the first eight data bytes (with user prmdata). The first seven bytes are specified according to the standard. The eighth byte is used for SPC3-specific characteristics. The additional bytes are available to the application.Byte

012345678-243Byte 7Bit012

LockReq

Unlo.Req

SyncReq

Bit Position43

FreeReq

WDon

Designation

Res

Station statusWD_Fact_1WD_Fact_2MinTSDR

Ident_Number_HighIdent_Number_LowGroup_Ident

Spec_User_Prm_ByteUser_Prm_Data

00000

WD_BaseDisStopDisStart

Spec_User_Prm_ByteNameSignificanceDis_StartbitThe start bit monitoring in the

receiver is switched off with this bit.Dis_StopbitWD_Base

Stop bit monitoring in the receiver isswitched off with this bit.

This bit specifies the time base usedto clock the watchdog.

WD_Base = 0: time base 10 msWD_Base = 1: time base 1 msto be parameterized with 0

Default StateDis_Startbit= 1 ,

that is, start bit monitoring isswitched off.Dis_Stopbit= 0,

that is, stop bit monitoring is notswitched off.WD_Base= 0,

that is, the time base is 10 ms0

3-7res

Figure 6.5: Data Format for the Set_Param_Telegram

6.2.2.2 Parameter Data Processing SequenceIn the case of a positive validatation for more than seven data bytes, SPC3 carries out the following reaction,among others:

SPC3 exchanges Aux-Puffer1/2 (all data bytes are input here) for the Prm buffer, stores the input data lengthin ‘R_Len_Prm_Data’, and triggers the ‘New_Prm_Data Interrupt’. The user must then check the‘User_Prm_Data’ and either reply with the ‘User_Prm_Data_Okay_Cmd’ or with‘User_Prm_Data_Not_Okay_Cmd.’ The entire telegram is input in the buffer, that is, application-specificparameter data are stored beginning with data byte 8 only.

The user response (User_Prm_Data_Okay_Cmd or User_Prm_Data_Not_Okay_Cmd) again takes backthe ‘New_Prm_Data’ interrupt. The user may not acknowledge the ‘New_Prm_Data’ interrupt in theIAR register.

The relevant diagnostics bits are set with the ‘User_Prm_Data_Not_Okay_Cmd’ message and are branchedto ‘Wait_Prm.’

The ‘User_Prm_Data_Okay’ and ‘User_Prm_Data_Not_Okay’ acknowledgements are reading accesses todefined registers with the relevant signals:• ‘User_Prm_Finished’: • ‘Prm_Conflict’ : • ‘Not_Allowed’,

SPC3 Hardware Description

No additional parameter telegram is present.

An additional parameter telegram is present, processing againAccess not permitted in the current bus state

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AddressControlRegister0EH

Bit Position430

1⇓

001

0⇓011

SPC3

Designation

User_Prm_Data_OkayUser_Prm_FinishedPRM_ConflictNot_Allowed

AddressControlRegister0FH

Bit Position430

Designation

1⇓

001

0⇓011

User_Prm_Data_Not_OkayUser_Prm_FinishedPRM_ConflictNot_Allowed

Figure 6.6: Coding User_Prm_Data_Not/_Okay_Cmd

If an additional Set-Param telegram is supposed to be received in the meantime, the signal ‘Prm_Conflict’ isis returned for the acknowledgement of the first Set_Param telegram, whether positive or negative. Then theuser must repeat the validation because the SPC3 has made a new Prm buffer available.6.2.3 Check_Config (SAP62)

The user takes on the evaluation of the configuration data. After SPC3 has received a validatedCheck_Config-Telegram, SPC3 exchanges the Aux-Puffer1/2 (all data bytes are entered here) for the Cfgbuffer, stores the input data length in ‘R_Len_Cfg-Data,’ and generates ‘New_Cfg_Data-Interrupt’.

The user must then check the ‘User_Config_Data’ and either respond with ‘User_Cfg_Data_Okay_Cmd’ orwith ‘User_Cfg_Data_Not_Okay_Cmd’ (acknowledgement to the Cfg_SM). The net data is input in the bufferin the format regulation of the standard.

The user response (User_Cfg_Data_Okay_Cmd or the User_Cfg_Data_Not_Okay_Cmd response)again takes back the ‘New_Cfg_Data’ interrupt and may not be acknowledged in the IAR.

If an incorrect configuration is signalled back, various diagnostics bits are changed, and there is branching to‘Wait_Prm.“

For a correct configuration, the transition to ‘DATA_EX’ takes place immediately, if no Din_buffer is present(R_Len_Din_Puf = 00H) and trigger counters for the parameter setting telegrams and configuration telegramsare at 0. Otherwise, the transition does not take place until the first ‘New_DIN_Puffer_Cmd’ with which theuser makes the first valid ‘N buffer” available. When entering into ‘DATA_EX,’ SPC3 also generates the‘Go/Leave_Data_Exchange-Interrupt.

If the received configuration data from the Cfg buffer are supposed to result in a change of the Read-Cfg-buffer ( the change contains the data for the Get_Config telegram), the user must make the new Read_Cfgdata available in the Read-Cfg buffer before the ‘User_Cfg_Data_Okay_Cmd” acknowledgement. Afterreceiving the acknowledgement, SPC3 exchanges the Cfg buffer with the Read-Cfg buffer, if‘EN_Change_Cfg_buffer = 1’ is set in mode register1.

During the acknowledgement, the user receives information about whether there is a conflict or not. If anadditional Check_Config telegram was supposed to be received in the meantime, the user receives the‘Cfg_Conflict” signal during the acknowledgement of the first Check_Config telegram, whether positive ornegative. Then the user must repeat the validation, because SPC3 has made a new Cfg buffer available.The ‘User_Cfg_Data_Okay_Cmd’ and ‘User_Cfg_Data_Not_Okay_Cmd’ acknowledgements are readaccesses to defined memory cells (see Section 2.2.1) with the relevant ‘Not_Allowed’, ‘User_Cfg_Finished,’or ‘Cfg_Conflict’ signals (see Figure 3.7). If the ‘New_Prm_Data’and ‘New_Cfg_Data’ are supposed to bepresent simultaneously during power up, the user must maintain the Set_Param and then theCheck_Config. acknowledgement sequence.

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Bit Position

V1.1

Designation

SPC3 Hardware Description

SPC3

ControlRegister10H

1⇓0011⇓001

0⇓0110⇓011

PROFIBUS Interface Center

User_Cfg_Data_OkayUser_Cfg_FinishedCfg_ConflictNot_AllowedDesignation

AddressControlRegister11H

Bit Position430

User_Cfg_Data_Not_Okay

User_Cfg_FinishedCfg_ConflictNot_Allowed

Figure 6.7: Coding of the User_Cfg_Data_Not/_Okay_Cmd

6.2.4 Slave_Diagnosis (SAP60)

6.2.4.1 Diagnostics Processing SequenceTwo buffers are available for diagnostics. The two buffers can have varying lengths. SPC3 always has onediagnostics buffer assigned to it, which is sent for a diagnostics call-up. The user can pre-process newdiagnostics data in parallel in the other buffer. If the new diagnostics data are to be sent now, the user usesthe ‘New_Diag_Cmd’ to make the request to exchange the diagnostics buffers. The user receivesconfirmation of the exchange of the buffers with the ‘Diag_Puffer_Changed Interrupt.’

When the buffers are exchanged, the internal ‘Diag_Flag’ is also set. For an activated ‘Diag_Flag,’ SPC3responds during the next Write_Read_Data with high-priority response data that signal the relevant masterthat new diagnostics data are present at the slave. Then this master fetches the new diagnostics data with aSlave_Diagnosis telegram. Then the ‘Diag_Flag” is reset again. If the user signals ‘Diag.Stat_Diag = 1,’however (static diagnosis, see the structure of the diagnostics buffer), then ‘Diag_Flag’ still remains activatedafter the relevant master has fetched the diagnosis. The user can poll the ‘Diag_Flag’ in the status register tofind out whether the master has already fetched the diagnostics data before the old data is exchanged for thenew data.

Status coding for the diagnostics buffers is stored in the‘Diag_bufferSM’ processor parameter. The user canread this cell with the possible codings for both buffers: ‘User,’ ‘SPC3,’ or ‘SPC3_Send_Mode.’AddressControlRegister0CH

Bit Position430

Designation

0D_Puf1

X1X2

Diag_Puffer_SM

See below for coding.

D_Puf2X1X2

X10011X20101Coding

Each for the D_Buf2 or D_Buf1UserSPC3

SPC3_Send_Mode

Figure 6.8: Diag_Buffer Assignment

The ‘New_Diag_Cmd’ is also a read access to a defined processor parameter with the signal as to whichdiagnostics buffer belongs to the user after the exchange, or whether both buffers are currently assigned toSPC3 (‘no Puffer’, ‘Diag_Puf1’, ‘Diag_Puf2’).

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AddressControlRegister0DH

Bit Position430

SPC3

Designation

1⇓

001

0⇓010

New_Diag_Cmdno PufferDiag_Puf1Diag_Puf2

Figure 6.9: Coding Diag_Puffer_SM, New_Diag_Cmd

6.2.4.2 Structure of the Diagnostics Buffer:The user transfers the diagnostics buffer displayed in the figure below to SPC3. The first 6 bytes are spaceholders, except for the three least significant bit positions in the first byte. The user stores the diagnosticsbits, ‘Diag.Ext_Diag’ ‘Diag.Stat_Diag,” and Diag.Ext.Diag_Overflow’ in these three bit positions. Theremaining bits can be assigned in any order. When sending, SPC3 pre-processes the first six bytescorresponding to the standard.Byte

Bit Position43

Designation

Ext_

DiagOverf

StatDiag

Ext_Diag

Spaceholder

123456-n

The user must input

SpaceholderSpaceholderSpaceholderSpaceholderSpaceholder

Ext_Diag_Data (n = max 243)

Figure 6.10: Structure of the Diagnostics Buffer for Transfer to the SPC3

The ‘Ext-Diag_Data’ the user must enter into the buffers follow after the SPC3-internal diagnostics data. Thethree different formats are possible here (device-related, ID-related, and port-related). In addition to the‘Ext_Diag_Data,’ the buffer length also includes the SPC3 diagnostics bytes (R_Len_Diag_Puf1,R_Len_Diag_Puf2).

6.2.5 Write_Read_Data / Data_Exchange (Default_SAP)

6.2.5.1 Writing OutputsSPC3 reads the received output data in the D buffer. After error-free receipt, SPC3 shifts the newly filledbuffer from ‘D’ to ‘N.’ In addition, the ‘DX_Out_Interrupt’ is generated. The user now fetches the currentoutput data from ‘N.’ The buffer changes from ‘N’ to ‘U’ with the ‘Next_Dout_Buffer_Cmd,’ so that the currentdata of the application can be sent back for the master’s Read_Outputs.

If the user’s evaluation cycle time is shorter than the bus cycle time, the user does not find any new bufferswith the next ‘Next_Dout_Buffer_Cmd’ in ‘N.’ Therefore, the buffer exchange is omitted, At a 12 Mbd baudrate, it is more likely, however, that the user’s evaluation cycle time is larger than the bus cycle time. Thismakes new output data available in ‘N’ several times before the user fetches the next buffer. It isguaranteed, however, that the user receives the data last received.

For ‘Power_On’, ‘Leave_Master’ and the Global_Control-Telegram ‘Clear,’ SPC3 deletes the D buffer andthen shifts it to ‘N.’ This also takes place during the power up (entering into ‘Wait_Prm’). If the user fetchesthis buffer, he receives the ‘U_buffer cleared’ display during the ‘Next_Dout_Buffer_Cmd.’ If the user is stillsupposed to enlarge the output data buffer after the Check_Config telegram, the user must delete this deltain the N buffer himself (possible only during the power-up phase in the ‘Wait_Cfg’ state).

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The user can read the buffer management state with the following codes for the four states: ‘Nil’,‘Dout_Puf_Ptr1-3’. The pointer for the current data is in the “N” state.AddressControlRegister0AH

Bit Position43U

NX2

Designation

DX20

Dout_Puffer_SM

See below for coding.

7FX1

X10011X20101CodingNil

Dout_Puf_Ptr1Dout_Puf_Ptr2Dout_Puf_Ptr3

Figure 6.11: Dout_Buffer Management

When reading the ‘Next_Dout_Buffer_Cmd’ the user gets the information which buffer (U-buffer) belongs tothe user after the change, or whether a change has taken place at all.AddressControlRegister0BH

Bit Position430

BufferCleared

Designation

State_U_Buffer

Next_Dout_Buf_CmdDout_Buf_Ptr1Dout_Buf_Ptr2Dout_Buf_Ptr3No new U bufferNew U buffer

U buffer contains dataU buffer was deleted

Ind_U_Buffer

01101

Figure 6.12: Next_Dout_Puffer_Cmd

101

The user must delete the U buffer during initialization so that defined (deleted) data can be sent for aRead_Output Telegram before the first data cycle.

6.2.5.2 Reading InputsSPC3 sends the input data from the D buffer. Prior to sending, SPC3 fetches the Din buffer from ‘N’ to ‘D.’ Ifno new buffer is present in ‘N,’ there is no change.

The user makes the new data available in ‘U’. With the ‘New_Din_buffer_Cmd,’ the buffer changes from ‘U’to ‘N’. If the user’s preparation cycle time is shorter than the bus cycle time, not all new input data are sent,but just the most current. At a 12 Mbd baud rate, it is more probable, however, that the user’s preparationcycle time is larger than the bus cycle time. Then SPC3 sends the same data several times in succession.During start-up, SPC3 first goes to ‘DATA_EX’ after all parameter telegrams and configuration telegrams areacknowledged, and the user then makes the first valid Din buffer available in ‘N’ with the‘New_Din_Buffer_Cmd.

If ‘Diag.Freeze_Mode = 1’, there is no buffer change prior to sending.

The user can read the status of the state machine cell with the following codings for the four states: ‘Nil’,‘Dout_Puf_Ptr1-3.’ (See Figure 3.13.) The pointer for the current data is in the “N” state.

SPC3 Hardware Description

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PROFIBUS Interface Center

AddressControlRegister08H

Bit Position43U

NX2

SPC3

Designation

7FX1

652

Din_Buffer_SM

See below for coding.

X10011X20101CodingNil

Din_Buf_Ptr1Din_Buf_Ptr2Din_Buf_Ptr3

Figure 6.13: Din_Buffer Management

When reading the ‘New_Din_Buffer_Cmd’ the user gets the information which buffer (U-buffer) belongs to theuser after the change (Din_Buf_Ptr 1-3).AddressControlRegister09H

Bit Position430

Designation

1⇓

011

0⇓101

New_Din_Buf_CmdDin_Buf_Ptr1Din_Buf_Ptr2Din_Buf_Ptr3

Figure 6.14: Next_Din_Buffer_Cmd

6.2.5.3 User_Watchdog_TimerAfter power-up (‘DATA_EX’ state), it is possible that SPC3 continually answers Write_Read_Data-telegramswithout the user fetching the received Din buffers or making new Dout buffers available. If the user processor‘hangs up,’ the master would not receive this information. Therefore, a ‘User_Watchdog_Timer’ isimplemented in SPC3.

This User_Wd_Timer is an internal 16-bit RAM cell that is started from a ‘R_User_Wd_Value15..0’ value theuser parameterizes and is decremented with each received Write_Read_Data telegram from SPC3. If thetimer attains the ‘0000hex’ value, SPC3 transitions to the ‘Wait_Prm’ state, and the DP_SM carries out a‘Leave_Master.’ The user must cyclically set this timer to its start value. Therefore, ‘Res_User_Wd = 1’ mustbe set in mode register 1. Upon receipt of the next Write_Read_Data telegram, SPC3 again loads theUser_Wd_Timer to the parameterized value ‘R_User_Wd_Value15..0’ and sets ‘Res_User_Wd = 0’ (ModeRegister 1). During power-up, the user must also set ‘Res_User_Wd = 1’, so that the User_Wd_Timer iseven set at its parameterized value.6.2.6 Global_Control (SAP58)

SPC3 itself processes the Global_Control-Telegrams in the manner already described. In addition, thisinformation is available to the user.

The first byte of a valid Global_Control command is stored in the R_GC_Comand RAM cell. The secondtelegram byte (Group_Select) is processed internally.

AddressRAMCell3CH

Res

Sync

Bit Position43

Unsync

Freeze

Designation

Unfreeze

Clear_Data

Res

R_GC_Command

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SPC3

Bit0123456,7

DesignationReservedClear_DataUnfreezeFreezeUnsyncSyncReserved

Significance

PROFIBUS Interface Center

With this command, the output data is deleted in ‘D’ and is changedto ‘N.’

With „Unfreeze,“ freezing input data is cancelled.

The input data is fetched from ‘N’ to ‘D’ and „frozen“. New input datais not fetched again until the master sends the next ‘Freeze’command.

The „Unsync“ command cancels the „Sync“ command.

The output data transferred with a WRITE_READ_DATA telegram ischanged from ‘D’ to ‘N.’ The following transferred output data is keptin ‘D’ until the next ‘Sync’ command is given.

The „Reserved“ designation specifies that these bits are reserved forfuture function expansions.

Figure 6.15: Data Format for the Global_Control Telegram

If the Control_Comand byte changed at the last received Global_Control telegram, SPC3 additionallygenerates the ‘New_GC_Command’ interrupt. During initialization, SPC3 presets the ‘R_GC_Command’RAM cell with 00H. The user can read and evaluate this cell.

So that Sync and Freeze can be carried out, these functions must be enabled in the mode register.6.2.7 Read_Inputs (SAP56)

SPC3 fetches the input data like it does for the Write_Read_Data Telegram. Prior to sending, ‘N’ is shifted to‘D,’ if new input data are available in ‘N.’ For ‘Diag.Freeze_Mode = 1,’ there is no buffer change.6.2.8 Read_Outputs (SAP57)

SPC3 fetches the output data from the Dout buffer in ‘U’. The user must preset the output data with ‘0’ duringstart-up so that no invalid data can be sent here. If there is a buffer change from ‘N’ to ‘U’ (through theNext_Dout_Buffer_Cmd) between the first call-up and the repetition, the new output data is sent during therepetition.

6.2.9 Get_Config (SAP59)

The user makes the configuration data available in the Read_Cfg buffer. For a change in the configurationafter the Check_Config telegram, the user writes the changed data in the Cfg buffer, sets‘EN_Change_Cfg_buffer = 1’ (see Mode-Register1), and SPC3 then exchanges the Cfg buffer for theRead_Cfg buffer. (See Section 3.2.3.) If there is a change in the configuration data (for example, for themodular DP systems) during operation, the user must return with ‘Go Offline’ (see Mode Register1) to‘Wait_Prm’ to SPC3.

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PROFIBUS Interface Center7 Hardware Interface7.1 Universal Processor Bus Interface

7.1.1 General Description

SPC3

SPC3 has a parallel 8-bit interface with an 11-bit address bus. SPC3 supports all 8-bit processors andmicrocontrollers based on the 80C51/52 (80C32) from Intel, the Motorola HC11 family, as well as 8-/16-bitprocessors or microcontrollers from the Siemens 80C166 family, X86 from Intel, and the HC16 and HC916family from Motorola. Because the data formats from Intel and Motorola are not compatible, SPC3automatically carries out ‘byte swapping’ for accesses to the following 16-bit registers (interrupt register,status register, and mode register0) and the 16-bit RAM cell (R-User_Wd_Value). This makes it possible fora Motorola processor to read the 16-bit value correctly. Reading or writing takes place, as usual, through twoaccesses (8-bit data bus).

Due to the 11-bit address bus, SPC3 is no longer fully compatible to SPC2 (10-bit address bus). However,AB(10) is located on the XINTCI output of the SPC2 that was not used until now. For SPC3, the AB(10) inputis provided with an internal pull-down resistor. If SPC3 is to be connected into existing SPC2 hardware, theuser can use only 1 kByte of the internal RAM. Otherwise, the AB(10) cable on the modules must be movedto the same place.

The Bus Interface Unit (BIU) and the Dual Port RAM Controller (DPC) that controls accesses to the internalRAM belong to the processor interface of the SPC3.

In addition, a clock rate divider is integrated that the clock pulse of an external clock pulse generator dividedby 2 (Pin: DIVIDER = High-Potential) or 4 (Pin: DIVIDER = Low-Potential) makes available on the pinCLKOUT2/4 as the system clock pulse so that a slower controller can be connected without additionalexpenditures in a low-cost application. SPC3 is supplied with a clock pulse rate of 48MHz.7.1.2 Bus Interface Unit (BIU)

The BIU forms the interface to the connected processor/microcontroller. This is a synchronous orasynchronous 8-bit interface with an 11-bit address bus. The interface is configurable via 2 pins (XINT/MOT,MODE). The connected processor family (bus control signals such as XWR, XRD, or R_W, and the dataformat) is specified with the XINT/MOT pin. Synchronous (rigid) or asynchronous bus timing is specified withthe MODE pin.

Various Intel system configurations are displayed in the figures in Section 7.1.3. The internal address latchand the integrated decoder must be used in the C32 mode. One figure displays the minimum configuration ofa system with SPC3, whereby the block is connected to an EPROM version of the controller. Only a pulsegenerator is necessary as an additional block in this configuration. If a controller is to be used without anintegrated program memory, the addresses must once again be latched off for the external memory. Theconnection schematic in the next figure is applicable for all Intel/Siemens processors that offer asynchronousbus timing and evaluate the ready signal.Notes:

If the SPC3 is connected to an 80286 processor, or others, it must be taken into consideration that theprocessor carries out word accesses. That is, either a “swapper” is necessary that switches the charactersout of the SPC3 at the relevant byte position of the 16-bit data bus during reading, or the least significantaddress bit is not connected, and the 80286 must read word accesses and evaluate only the lower byte, asdisplayed in the figure.

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V1.1SPC3 Hardware Description

SPC3

XINT/MOMODE

11synchron-ousMotorola

PROFIBUS Interface Center

10asynchron-ousMotorola

0synchron-ousIntel

asynchron.Intel

The SPC3 interface supports the following processors/microcontrollers.Motorola microcontroller with the following characteristics:

• Synchronous (rigid) bus timing without evaluation of the XREADY signal• 8-bit non-multiplexed bus: DB7..0, AB10..0The following can be connected:• HC11 types: K, N, M, F1

• HC16- und HC916 types with programmable E clock timing

• All other HC11 types with a multiplexed bus must select addresses AB7..0 externallyfrom DB7..0 data.

The address decoder is switched off in the SPC3. The CS signal is fed to SPC3.

• For microcontrollers with chip select logic (K, F1, HC16, and HC916), the chip selectsignals are programmable as regards the address range, the priority, the polarity, andthe window width in the write cycle or read cycle.

• For microcontrollers without chip select logic (N and M), and others, an external chipselect logic is required. This means additional hardware and a fixed assignment.Condition:

• The SPC3 output clock (CLKOUT2/4) must be four times larger than the E_CLOCK.The SPC3 input clock (CLK) must be at least 10 times larger than the desired systemclock (E_Clock). The divider pin must be placed at „low“ (divider 4), and it results in anE_CLOCK of 3 MHz

Motorola microcontroller with the following characteristics:

• Asychronous bus timing with evaluation of the XREADY signal• 8-bit non-multiplexed bus: DB7..0, AB10..0The following can be connected:• HC16 and HC916 types

• All other HC11 types with a multiplexed bus must externally select addresses AB7..0from data DB7..0.

The address decoder is switched off in SPC3. The CS signal is fed into SPC3.• Chip select logic is available and programmable in all microcontrollers.Intel microcontroller CPU basis is 80C51/52/32, microcontrollers from variousmanufacturers:

• Sychronous (rigid) bus timing without evaluation of the XREADY signal• 8-bit multiplexed bus: ADB7..0The following can be connected:

• Microcontroller families from Intel, Siemens, and Philips, for exampleThe address decoder is switched on in SPC3. The CS signal is generated for SPC3internally.

• The lower address bits AB7..0 are stored with the ALE signal in an internal addresslatch. The internal CS decoder is activated in SPC3 that generates its own CS signalfrom the AB10..0 addresses.

• The internal address decoder is fixed wired, so that SPC3 must always be addressedunder the fixed addresses AB7..0 = 00000xxxb. SPC3 selects relevant address windowfrom the AB2..0 signals. In this mode, the CS-Pin (XCS) must be located at VDD (highpotential).

Intel- and Siemens 16-/8-bit microcontroller families

• Asychronous bus timing with evaluation of the XREADY signal• 8 bit non-multiplexed bus: DB7..0, AB10..0The following can be connected:

• Microcontroller families from Intel x86 and Siemens 80C16x, for exampleAddress decoder is switched off in SPC3. The CS signal is fed in to the SPC3.• External address decoding is always necessary.

• External chip select logic if the microcontroller is not presentFigure 7.1: Bus Interface

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PROFIBUS Interface Center

7.1.3 Switching Diagram Principles

SPC3

Low Cost System with 80C3212/24 MHzCLKWRRDINT0Pulse Generator48MHzDIVIDERXWRXRDX/INTDB 7..0DataDivider:2/4RTSTxDRxDXCTS80C32/C501Port 0ALEA / D 7...0DB 7..0Address LatchPort 2AB 15...8(0000 00XXBIN)AB 7..0AddressdecoderSPC31KGNDAB8AB9AB10ModeResetSPC3Reset1K1K1K3K3VDDGND80C32 System with Ext. Memory (C32-Mode)12/24 MHzCLKPulse Generator48 MHzDIVIDERWRRDINT0XWRXRDX/INTDB 7..0DataScaler:2/4RTSTxD80C3220/16MHzRxDXCTSALEDB 7..0Address LatchPort 0Port 2PSENA / D 7...0AB 15...8AddressLatch(0000 00XXBIN)AB 7....0Address-decoderSPC31KGNDAB 15...0ResetAB8AB9AB10ModeSPC3ResetEPROM64kBRAM32kBRD WRAddressDecoder1K1K1KGND3K3VDDPage 38

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V1.1SPC3 Hardware Description

SPC3

80286-System (X86-Mode)PROFIBUS Interface Center

Clock -Generator48 MHz12/24 MHzDIVIDERCLKWRRDINTRREADY-LogicXWRXRDX/INT TeilerRTSTxDRxDXREADY80286+Buscontr.(82288) +82244DBDB 15...0DB 7...0DB(7..0)XCTSSPC3AB(10..01KGNDABAB 23...0AB 12...1RDWRResetDriver, Control-logicCSRAMXCSCSEPROMModeSPC3ResetEPROM64kBRAM32kBAddressDecoderCS3K3GND

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PROFIBUS Interface Center

7.1.4 Application with the 80 C 32

SPC3

548 MHzMuCPx.x1K836CLKSPC3CLK2XHOLDT.XREADY713XINT/MOTRESETP5P5uCuCuCP5ALEXWRXRD3k33k31232424XCSMODEALEXWRXRDXTEST0141091KMINT0/1AB 10X/INTuC3k33k35V orGNDAB8AB9343534443XCTSRXDRTS333027261KRXDRTSTXDP5XTEST1DIVIDER012RS485RS485RS485TXDAB10AB11AB12AB13AB14ADB(8:15)AB15MM1K1414037423231012345111215161920ADB0ADB1ADB2ADB3ADB4ADB534567ABDBuC292589672122ADB6ADB71KDB(0:7)uCThe pull up / pull down resistances in the drawing above are only relevant for a in circuit tester.The internalchip select logic is activated when the address pins A 11 .. A 15 are set to „0“ . In the example above thestarting address of the SPC3 is set to 0x1000 .

ProcessorALESPC 3Addreß-AD 0 ..7latchA 0..101,5 kByte RAM in the SPC 3AD 0 ..7A8 .. 10A 11..15 alle 0CSPage 40

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SPC3

7.1.5 Application with th 80 C 165

PROFIBUS Interface Center

548 MHzMuCuC1KXSPC3CS83612324243k33k35V orgroundAB0AB1AB2AB3AB4AB5AB6AB7AB8AB(0:10)uCAB9AB10343534443414037423231292510CLKSPC3CLK2XDATAEX.XREADY713149XREADYXEXxINuCuCXINT/MOTRESETXCSMuCuCuCP5P5M1K1KXWRLXRDMODEALEXWRXRDXTEST0XTEST1DIVIDER012345678910ABDB012345671112151619202122DB0DB1DB2DB3DB4DB5DB6DB7RXDRTSTXD302726RXDRTSTXDRS485RS485RS485XCTS331KXINTDB(0:7)uCThe pull up / pull down resistances in the drawing above are only relevant for a in circuit tester.Dual Port RAM Controller

The internal 1.5k RAM of the SPC3 is a Single Port RAM. Due to an integrated Dual Port RAM controller, thecontroller, however, permits an almost simultaneous access of both ports (bus interface and microsequencerinterface). When there is a simultaneous access of both ports, the bus interface has priority. This providesfor the shortest possible access time. If SPC3 is connected to a microcontroller with an asynchronousinterface, SPC3 can evaluate the Ready signal.

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PROFIBUS Interface Center

7.1.6 Interface Signals

SPC3

The data bus outputs are high-resistance during the reset phase. All outputs are switched to high-resistancein the test mode. (See block test.)Name

Input/Output

DB(7..0)I/OAB(10..0)IMODEIXWR/E_CLOCKIXRD/R_WIXCSIALE/ASIDIVIDERIX/INTOXRDY/XDTACKOCLKIXINT/MOTICLKOUT2/4ORESETI

TypeTristate

Comments

High-resistance for RESET

AB(10) has a pull down resistor.Setting: syn/async interfaceIntel: Write /Motorola: E-Clk

Intel: Read /Motorola: Read/WriteChip Select

Intel/Motorola: Address Latch EnableScaling factor 2/4 for CLKOUT 2/4

TristatePolarity programmableTristateIntel/Motorola: Ready-Signal

48 MHz

Setting: Intel/Motorola

Tristate24/12 MHz

Schmitt-TriggerMinimum of 4 clock pulse cycles

Figure 7.2: Microprocessor Bus Signals

7.2 UART

The transmitter converts the parallel data structure into a serial data flow. Request-to-Send (RTS) isgenerated before the first character. The XCTS input is available for connecting a modem. After RTS active,the transmitter must hold back the first telegram character until the XCTS modem activates.

The receiver converts the serial data flow into the parallel data structure. The receiver scans the serial dataflow with the four-fold transmission speed. Stop bit testing can be switched off for test purposes(„DIS_STOP_CONTROL = 1“, in mode register 0 or ‘Set_Param-Telegram’ for DP). One requirement of thePROFIBUS protocol is that no rest states are permitted between the telegram characters. The SPC3transmitter ensures that this specification is maintained. This following start bit test is switched off with theparameter setting „DIS_START_CONTROL = 1“ (in mode register 0 or ‘Set_Param telegram’ for DP).Specified by the four-fold scan, a maximum distortion of the serial input signal of X = -47% to y = +22% ispermissible.

7.3 ASIC Test

All output pins and I/O pins can be switched in the high-resistance state via the XTESTO test pin. Anadditional XTEST1 input is provided (more information upon request) to test the block internally with testautomatic devices (not in the target hardware environment!).Pin No.3435

NameXTEST0XTEST1

FunctionVSS (GND)VDD (+5V)VSS (GND)VDD (+5V)

All outputs high-resistanceNormal SPC3 functionVarious test modesNormal SPC3 function

Figure 7.3: Test Support

XTEST0 and XTEST1 must be placed on VDD (+5V) via external pull-up resistors.

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SPC3

8 Technical Data8.1 Maximum Limit Values

Parameter

DC supply voltageInput voltageOutput voltageDC output currentDC supply currentStorage temperatureAmbient temperature

DesignationVDDVIVOIOIDD,ISSTstgTopt

Limits-0.5 to 7-0.5 to VDD +0.5-0.5 to VDD +0.5See Section 5.4.

TBD40 to +125-40 to +85

PROFIBUS Interface Center

UnitVVVmAmA°C°C

8.2 Typical Values

Parameter

Current consumption duringRESET

Current consumption without busaccesses

Current consumption using 12Mbaud bus accessesThermal resistance

Designation

IaIaIaRw

Limits5810211065

UnitmAmAmAK/W

8.3 Permitted Operating Values

Parameter

Supply Voltage (5V)(VSS = 0V)Input voltage

Input voltage (high-level)Input voltage (low-level)Output voltage

DC Supply current typ.Operating temperature

Designation

VDDVIVIHVILVOIDD,ISSTA

MIN4.7500.7 VDD

MAX5.25VDDVDD0.3 VDDVDD

UnitVVVVVmA°C

-40+85

8.4 Ratings for the Output Drivers

Signal CableDB 0-7RTSTxDX/INT

XREADY/XDTACKXDATAEXCHXHOLD-TOKENCLKOUT2/4

DirectionI/OOOOOOOO

DriverTypeTristateTristateTristateTristateTristateTristateTristateTristate

Driver Strength

8mA8mA8mA4mA4mA8mA8mA8mAV1.1

Capacitive Load

100pF50pF50pF50pF50pF50pF50pF100pF

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SPC3 Hardware Description

PROFIBUS Interface Center

8.5 DC Specification for the I/O Drivers

Parameter

CMOS input voltage 0signal level

CMOS input voltage 1signal level

CMOS output voltage 0signal level

CMOS output voltage 1signal level

CMOS Schmitt Trigger +vethreshold

CMOS Schmitt Trigger -vethreshold

TTL Schmitt Trigger +vethreshold

TTL Schmitt Trigger -vethreshold

Input leakage currentTristate output leakagecurrent

Output current 0 signallevel4mA cell

Output current 1 signallevel4mA cell

Output current 0 signallevel8mA cell

Output current 1 signallevel8mA cell

Short-circuit currentInput capacityOutput capacityI/O capacity

Designation

VILCVIHCVOLVOHVT+VT-VT+VT-IIIOZIOLIOHIOLIOHIOSCinCoutCI/O

4-88-83000.61.0VDD-0.5MIN00.7 VDD

SPC3

TYPEMAX0.3 VDDVDD0.4 * *

UnitVVVVVV

3.01.52.00.8

4.0

2.4VV

±1±10

µAµAmAmAmAmAmA

101010

pFpFpF

• for a specified output load (4/8mA)

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V1.1SPC3 Hardware Description

SPC3

8.6 Timing Characteristics

PROFIBUS Interface Center

The following is generally applicable: All signals beginning with ‘X’ are ‘low active’.All signal runtimes are based on the capacitive loads specified in the table above.

8.6.1 SYS Bus InterfaceClock Pulse:No.1234

Parameter

Clock pulse 48 Mhz :Clock High TimeClock Low Time RiseTimeFall Time

MIN6.256.25

MAX14.614.644

Unitnsnsnsns

Clock Pulse Timing:

Verzerrungen des Taktsignals sind bis zu einem Verhältnis von 40:60 zugelassen. Bei einer Schwelle von 1,5 bzw. 3,5V:

TCLHTCLL12CLK

Distortions in the clock pulse signal are permitted up to a ratio of 40:60. At a threshold of 1.5 or 3.5 V:Interrupts:No.1

Parameter

Interrupt Inactive Time (for EOI_Timebase = 0)Interrupt Inactive Time

MIN11

MAX11

Unitµsms

X/INT 1EOI

After acknowledging an interrupt with EO1, a min. of 1 us or 1 ms is expected in SPC3 before a new interrupt

is output.Reset:

SPC3 requires a minimum of 400 clock pulse cycles during the reset phase so that it can be reset correctly.Reset

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PROFIBUS Interface Center

8.6.2 Timing in the Synchronous C32-Mode:

SPC3

If SPC3 is operated at 48MHz, an 80C32 with a maximum clock pulse rate of 20MHz can be connected.In the C32 mode, SPC3 saves the least significant addresses with the negative edge of ALE. At the sametime, SPC3 expects the more significant address bits on the address bus. SPC3 generates a chipselectsignal from the more significant address bits. The request for an access to SPC3 is generated from thenegative edge of the read signal and from the positive edge of the write signal.No.123

Parameter

Address to ALE 󰂔 Setup Time

Address (A7..0) Hold after XRD or XWR Æ

XRD Ç to Data Out XRD Ç to Data Out ALE Ç to XRD Ç

Data Holdtime after XRD ÆData Holdtimeafter XWR ÆData Setuptime to XWR ÆXRD Æ to ALE ÆXRD-Pulse-WidthXWR-Pulse-Width

Address Hold after ALE 󰂔ALE-Pulsewidth

XRD, XWR CycletimeALE Ç to XWR ÇXWR Æ to ALE Æ

MIN105

MAXUnitnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

3T+42.5

(105)4T+20.2

203.11010106T-103T10106T+302010

10.2

4567810111213141516

Explanations:TTBD

(1(2(3)

=====Clock pulse cycle (48MHz)to be defined

Access to the RAM

Access to the registers/latchesfor T = 48MHz

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C32-Mode, Prozessor-Read-Timing (XWR = 1)

13PROFIBUS Interface Center

ALE

112 2AB 7..0

VALIDDB 7..0

Adressen 3Data Out510AdressenXRD

14C32-Mode, Prozessor-Write-Timing (XRD = 1)

1314ALE

112 2AB 7..0

VALIDVALIDDB 7..0AdressenData In 7 6AdressenXWR

1114SPC3 Hardware Description

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PROFIBUS Interface CenterSPC3

8.6.3 Timing in the Asynchronous Intel Mode (X86 Mode) :

In 80X86 operation, SPC3 acts like memory with ready logic. The access times depend on the type ofaccesses.

The request for an access to SPC3 is generated from the negative edge of the read signal or the positiveedge of the write signal.

SPC3 generates the Ready signal synchronously to the fed in pulse. The Ready signal is reset when theread signal or write signal is deactivated. The data bus is switched to the Tristate with XRD = 1.Nr.2021

Parameter

Address-Setuptime to XRD or XWR Ç

XRD Ç to Data valid

Address (A10..0) Hold after XRD or XWR ÆXCS Ç Setuptime to XRD Ç or WR ÇXRD Pulse-Width

Data Holdtime after XRD ÆRead/Write-Inactive-Time

XCS Holdtime after XRD or XWR ÆXRD Ç to XRDY Ç (Normal Ready)XRD Ç to XRDY Ç (Early Ready)XREADY-Holdtime after XRD or XWRData Setuptime to XWR ÆData Holdtime after XWR ÆXWR-Pulse-WidthXRD, XWR Cycletimelast XRD Ç to XCS ÇXCS Æ to next XWR Æ

XWR Æ to next XWR Æ (XCS don’t care)

MIN0

MAX3T+42,5

(105)3T+18

Einh.nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

22232425262728293031323334353637

0-56T-103.1100

10.2

610104T6T4T+102T+106T

5T+164T+1222

Explanations:TTBD

(1(2(3

=====Clock pulse cycle (48MHz)to be defined

Access to the RAM

Access to the registers/latchesFor T = 48 MHz

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V1.1SPC3 Hardware Description

SPC3

X86-Mode, Prozessor-Read-Timing (XWR = 1)

AB 10..0PROFIBUS Interface Center

VALID202122DB 7..024Data Out25XRD

352326XCS

27XREADY(normal)283029XREADY(early)34X86-Mode, Prozessor-Write-Timing (XRD = 1)

AB 10..0

VALID2022DB 7..0

Data Out3132XWR

3326XCS

232736XREADY(normal)292830XREADY(early)

3437SPC3 Hardware Description

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PROFIBUS Interface CenterSPC3

8.6.4 Timing in the Synchronous Motorola Mode (E_Clock-Mode, for example, 68HC11) :

For a CPU clockline through the SPC3, the output clock pulse (CLKOUT2/4) must be 4 times larger than theE_CLOCK. That is, a clock pulse signal must be present at the CLK input that is at least 10 times largerthan the desired system clock pulse (E_CLOCK). The Divider-Pin must be placed on (divider 4).This results in an E_CLOCK of 3MHz.

The request for a read access to SPC3 is derived from the positive edge of the E clock (in addition: XCS = 0,R W = 1). The request for a write access is derived from the negative edge of the E clock (in addition: XCS =0, R W = 0).No.4041424344

Parameter

E_CLOCK-Pulse_Width

Address (A10..0) Setuptime to E_CLOCK 󰂒Address (A10..0) Holdtime to E_CLOCK 󰂔E_CLOCK 󰂒 to Data Active Delay

E_CLOCK 󰂒 to Data valid E_CLOCK 󰂒 to Data valid

Data Holdtime after E_CLOCK 󰂔R_W Setuptime to E_CLOCK 󰂒R_W Holdtime to E_CLOCK 󰂔XCS Setuptime to E_CLOCK 󰂒XCS Holdtime to E_CLOCK 󰂔Data Setuptime to E_CLOCK 󰂔Data Holdtime after E_CLOCK 󰂔

MIN3T+74.21052

MAXUnitnsnsnsnsnsnsnsnsnsnsnsnsns

454647484950514105001010

3+44.2

(107)4T+21.912

Explanations:TTBD

(1(2(3

=====Clock pulse cycle (48MHz)to be defined

Access to the RAM

Access to the registers/latchesFor T = 48 MHz

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V1.1SPC3 Hardware Description

SPC3

sync. Motorola-Mode, Prozessor-Read-Timing (AS = 1)

40PROFIBUS Interface Center

E_CLOCK414442AB 10..0

43VALID45DB 7..0

46Data InvalidData Valid47R_W

XCS

4849sync. Motorola-Mode, Prozessor-Read-Timing (AS = 1)

40E_CLOCK4142AB 10..0

VALID5051DB 7..0

46Data Valid47R_W

XCS

4849SPC3 Hardware Description

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PROFIBUS Interface CenterSPC3

8.6.5 Timing in the Asynchronous Motorola-Mode (for example, 68HC16) :

In the asynchronous Motorola mode, the SPC3 acts like memory with Ready logic, whereby the access timesdepend on the type of accesses.

The request for an access of SPC3 is generated from the positive edge of the AS signal (in addition:XCS=´0´, R_W=´1´). The request for a write access is generated from the positive edge of the AS signal (inaddition: XCS=´0´, R_W=´0´).Nr.6061

Parameter

Address-Setuptime to AS Ç

AS Ç to Data valid

Address (A10..0) Holdtime after ASÆR_W Ç Setuptime to AS ÇAS-Pulse-Width (Read)Data Holdtime after AS ÆAS-Inactive-Time

R_W Holdtime after AS ÆXCS Ç Setuptime to AS ÇXCS Holdtime after AS Æ

AS Ç to XDTACK Ç (Read, Normal Ready)AS Ç to XDTACK Ç (Read, Early Ready)XDTACH-Holdtime after AS ÆAS Cycletime

Data Setuptime to AS ÆData Holdtime after AS ÆAS-Pulse-Width (Write)last AS Ç (Read) to XCS ÇXCS Æ to next AS Æ (Write)

AS Æ to next AS Æ (Write, XCS don’t care)

MIN0

MAX3+45.2

(108)4T+22.9

Einh.nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

626364656667686970717273747576777879

10106T-1041010-50

66T10104T4T + 102T + 106T

5T+164T+1622

Explanations:TTBD

(1(2(3

=====Pulse cycle (48MHz)To Be Defined

Access to the RAM

Access to the register/latchesFor T = 48MHz

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SPC3

async. Motorola-Mode, Prozessor-Read-Timing (E_CLOCK = 0)AB 10..0PROFIBUS Interface Center

VALID606162DB 7..064Data Out65AS

6366R_W

7767XCS

6869XDSACK(normal))717072XDSACK(early)

73async. Motorola-Mode, Prozessor-Write-Timing (E_CLOCK = 0) AB 10..0VALID6062DB 7..0Data In74767579AS

666367R_W

686970727178XCS

XDSACK(normal)XDSACK(early)

73SPC3 Hardware Description

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PROFIBUS Interface Center

8.6.6 Serial Bus InterfaceNo.12T =

Parameter

Pulse 48 MHz:

RTS 󰂒 to TxD Setup TimeRTS 󰂔 to TxD Hold TokenClock pulse cycle (48MHz)

MIN4T4T

SPC3

MAXUnit

RTS

12TxD

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V1.1SPC3 Hardware Description

SPC3

8.6.7 Housing

PROFIBUS Interface Center

PQFP-44 Gehäuse

AB33342322C D4411112HGEM

FABA CB C DD EE FF GG HH LL MM 13,90 +-0,2510,00 +-0,1014,2 + 0,3 mm10,00+-0,109,88 + 0,15 mm14,2 + 0,3 mm13,90 +-0,259,88 + 0,15 mm02,00 +-0,102,03 + 0,1 mm00,88 +0,15 -0,108,81 + 0,03 mm00,800,8 mm00,35 +-0,050,36 + 0,01 mm00,25 min0,15 bis 0,30 mm00,17 max0,15 + 0.05 - 0.02 mm (Pindicke)LSPC3 Hardware Description

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PROFIBUS Interface Center

8.6.8 Processing Instructions

SPC3

ESD protective measures must be maintained for all electronic components.SPC3 is a cracking-endangered component that must be handled as such.

A drying process must be carried out before SPC3 is processed. The component must be dried at 125o Cfor 24 hours and then be processed within 48 hours. This drying process may be carried out once onlybecause the component is soldered.

It must also be ensured that the SPC3’s connections are not bent. Flawless processing can be guaranteedonly if a planity of less than 0.1 mm is ensured. SPC3 is released for infrared soldering with a solderingprofile according to CECC00802.

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SPC3

9 PROFIBUS Interface9.1 Pin Assignment

PROFIBUS Interface Center

The data transmission is performed in RS 485 operating mode (i.e., physical RS 485).

The SPC3 is connected via the following signals to the galvanically isolated interface drivers.Signal Name RTS TXD RXD

Input/OutputOutputOutputInput

Function Request to send Sending data Receiving data

The PROFIBUS interface is a 9-way, sub D, plug connector with the following pin assignment.Pin 1 - FreePin 2 - FreePin 3 - B line

Pin 4 - Request to send (RTS)Pin 5 - Ground 5V (M5)

Pin 6 - Potential 5V (floating P5)Pin 7 - FreePin 8 - A linePin 9 - Free

The cable shield must be connected to the plug connector housing.

The free pins are described as optional in EN 50170 Vol. 2. If used, they should conform to the specificationsin DIN192453.

CAUTION:

The designations A and B of the lines on the plug connector refer to the designations in the RS 485 standard,and not the pin designation of driver ICs.

Keep the cable from driver to connector as short as possible.

Use of higher baud rates )i.e., 3 to 12 Mbaud) requires the use of new plug connectors. These connectorscompensate for line interferences on all possible combinations of cables. 6ES7 972-0BB10-0XA0 with PG socket 6ES7 972-0BA10-0XA0 without PG socket

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9.2 Example for the RS 485 Interface

SPC3

2567341B - line2P5A - lineRTS2P52M89300R100K100KSN65ALS1176Driver select :Differential voltage > 2V112MImportant: electrical isolation to busP5 and 2P5U+EN1GNDEN222P568n74HC1322P52M2P5680R1K222M2M&300R1M1K268n68nHCPL0601680R680RU+HCPL7101 / 7721 / 0721ENENU+U-HCPL7101 / 7721 / 0721300RMOUTIN68n300RM20KP5P568nRTS CTS TXD M680RMExplanations of the circuitry:

The bus driver input EN2 has to be connected to low potential to ensure that after transmission of a telegramthe ASIC is able to listen to the transmitted data.

To minimize the capacity of the bus lines the user should avoid additional capacities. The typical capacity of abus station should be 15 ... 25 pF.

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RXD OUTU+U+ENU-U-INU-2.2 .. 22nF500 V680RSPC3 Hardware Description

Layout : lines must be kept as short as possible.ShieldSPC3

10 Appendix10.1 Addresses

PROFIBUS Trading OrganisationPNO

GeschäftsstelleHr. Betz

Haid- und Neu- Straße 776131 Karlsruhe

Tel.: (0721) 9658-590

Technical contact person in the Interface Center in GermanySiemens AGA&D SE E73Mr. MittelbergerAddress:

Würzburgerstr.12190766 Fürth

Tel.: (0911) 750 - 2072Fax: (0911) 750 - 2100Mailbox: (0911) -737972

eMail: Martin.Mittelberger@fthw.siemens.de

PROFIBUS Interface Center

Technical contact person in the Interface Center USAPROFIBUS Interface Center3000 Bill Garland Road

Johnson City, TN 37605-1255Fax : (423) - 461 - 2016BBS: (423) - 461 - 2751

Your Partner: Bernd ManglerTel.: (423) - 461 - 2332

eMail: Bernd.Mangler@sea.siemens.com

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PROFIBUS Interface Center

10.2 General Definition of Terms

ASPC2SPC2SPC3SPM2LSPM2DPFMSMSSM

SPC3

Advanced Siemens PROFIBUS Controller, 2 generation

Siemens PROFIBUS Controller, 2 generation

Siemens PROFIBUS Controller, 3 generation

Siemens PROFIBUS Multiplexer, 2 generation

Lean Siemens PROFIBUS Multiplexer, 2 generationDistributed I/Os

Fieldbus Message SpecificationMicroSequenzerState Machine

10.3 Ordering of ASICs

For Ordering SPC3 ASICs please refer to your contact person in the Siemens local branch office and useone of the ordering numbers depending on the amount you want to order.ASIC SPC 3(STEP C)

6ES7 195-0BD01-0XA06ES7 195-0BD11-0XA06ES7 195-0BD21-0XA06ES7 195-0BD31-0XA06ES7 195-0BD41-0XA0

small amountSingle l-TrayTray-Box8 Tray-Box17 Tray-Box

59657646089792

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SPC3PROFIBUS Interface Center

11 Appendix A: Diagnostics Processing in PROFIBUS DP11.1 Introduction

PROFIBUS DP offers a convenient and multi-layer possibility for processing diagnostics messages on thebasis of error states.

As soon as a diagnostics request is required, the slave will respond in the current data exchange with a highpriority reply message. In the next bus cycle, the master then requests a diagnostics from this slave, insteadof executing normal data exchange.

Likewise, any master (not only the assigned master!) can request a diagnostics from the slave. Thediagnostics information of the DP slave consists of standard diagnostics information (6 bytes), and can besupplemented by user-specific diagnostics information.

In the case of the ASICs, SPM2, and LSPM2, extensive diagnostics is possible through corresponding wiring.In the case of the intelligent SPCx solution, adapted and convenient diagnostics processing can be carriedout through programming.

11.2 Diagnostics Bits and Expanded Diagnostics

Parts of the standard diagnostics information are permanently specified in the firmware and in the micro-program of the ASICs through the state machine.

Request diagnostics only once („update_diag(..)“) if an error is present or changes. By no means shoulddiagnostics be requested cyclically in the data exchange state; otherwise, the system will be burdened byredundant data.

Three information bits can be influenced by the application:11.2.1 STAT_DIAG

Because of a state in the application, the slave can’t make valid data available. Consequently, the masteronly requests diagnostics information until this bit is removed again. The PROFIBUS DP state is, however,Data_Exchange, so that immediately after the cancellation of the static diagnostics, data exchange can start.Example: failure of supply voltage for the output drivers11.2.2 EXT_DIAG

If this bit is set, a diagnostics entry must be present in the user-specific diagnostics area. If this bit is notset, a status message can be present in the user-specific diagnostics area.User-Specific Diagnostics

The user-specific diagnostics can be filed in three different formats:Device-Specific Diagnostics:

The diagnostics information can be coded as required.Header Byte

Diagnostics Field.....

Bit 7Bit 6Bit 5-0

Block length in bytes, including header00

Coding of diagnostics is device-specificCan be specified as required

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Identifier-Related Diagnostics:

SPC3

For each identifier byte assigned during configuration (for example, 0 x 10 for 1 byte input), a bit is reserved.In the case of a modular system with an identifier byte each per module, module-specific diagnostics can beindicated. One bit respectively will then indicate diagnostics per module.Header ByteBit Structure

Bit 701

Bit 61

Bit 5-0

Block length in bytes including header

etc. ⇑ Identifier Byte 0 has

diagnostics

⇑ Identifier Byte 7 has

diagnostics

Channel-Related Diagnostics:

In this block, the diagnosed channels and the diagnostics cause are entered in sequence. Three bits arerequired per entry.Header Byte

Channel NumberType of Diagnostics

Bit 7Bit 6Bit 5Bit 4 - 0

Identification Number10

CodingChannel NumberInput/OutputCodingCodingChannel TypeError Type

Coding of the error type is in part manufacturer-specific; other codings are specified in the Standard.Example:

00000100

Device-specificdiagnostics field oflength 3

01000101

Device-related diagnostics.Meaning of the bitsis specified

manufacturer-specific.

Identifier-related diagnostics.

Identification number 0 has diagnostics.Identification number 18 has diagnostics.

100101000000000001001000000100001111010011000001Channel-related diagnostics, identification number 0.Channel 2.

Overload, channel organized bit by bit.

Channel-related diagnostics identification number 12.Channel 6.

Upper limit evalue xceeded, channel organized word by word.

Status

If the Bit EXT_DIAG is set to 0 , data is viewed as status info from the system view. f.e. cancellation of theerror triggering the diagnostics.

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11.2.3 EXT_DIAG_OVERFLOW

PROFIBUS Interface Center

This bit is set if more diagnostics data is present than will fit in the available diagnostics data area. Forexample, more channel diagnostics could be present than the send buffer or the receive buffer makespossible.

11.3 Diagnostics Processing from the System View

Inasmuch as it is bus-specific, the diagnostics information of the slaves is managed solely by the masterinterface (for example, IM308B).

All diagnostics from the application are made available to the S6 program via corresponding data bytes. Ifthe External Diagnostics bit is set, the slaves to be diagnosed can already be evaluated in the diagnosticsoverview. Then, a special error routine can be called up, whereby the standard diagnostics information andthe user-specific information can be evaluated.

After eliminating the current diagnostics situation, this can be signalled as a status message from the slavewithout setting the external diagnostics bit.

With the COM ET200, a comfortable diagnostics tool is available on-line. At the present time, identification-related diagnostics information can be displayed with it in plain text. In later phases, channel-relateddiagnostics will also be supported. User-specific diagnostics are only displayed if the EXT_DIAG bit is set.The figure below shows a screen during data processing, for example:Set Program File

SINGLE DIAGNOSTICSStation Number: 30Station Designation:Station Status:

C:PNO4..ET.200

SIMATIC S5 / COM ET 200Station Type: ET 200U-COMBI

Station4

Slave not ready for dataexchange

External diagnosticsConfiguration error

Device-Related Diagnostics

KH = 01

Identification-RelatedDiagnostics

Slot 3

ActiveF1

F8EXIT

In the type file for the COM ET200 and in the GSD [device master data] file, fields are already provided forreferencing device-specific bits and pertinent plain text messages (for example, Bit 7: „I have had it; goodnight!“).

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PROFIBUS Interface Center12 Appendix B: Useful InformationSPC3

12.1 Data format in the Siemens PLC SIMATIC

The SPC3 always sends data from the beginning of the buffer till the end. 16Bit values are shown in theMotorola format. For example:Buffer pointerBuffer pointer +1

high bytelow byte

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Siemens AG

Division Automation EngineeringCombination Engineering

PO Box 23 55, D-90713 Fuerth/Germany

Subject to change without prior noticePrinted in the Fed. Rep. of Germany

SIEMENS Aktiengesellschaft

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