—Military: 25/35/55ns (max.)
—Commercial: 20/25/35/55ns (max.)•Low-power operation—IDT7026S
Active: 750mW (typ.)Standby: 5mW (typ.)—IDT7026L
Active: 750mW (typ.)Standby: 1mW (typ.)
•Separate upper-byte and lower-byte control formultiplexed bus compatibility
•IDT7026 easily expands data bus width to 32 bits ormore using the Master/Slave select when cascadingmore than one device
•M/S = H for BUSY output flag on Master,M/S = L for BUSY input on Slave•On-chip port arbitration logic
•Full on-chip hardware support of semaphore signalingbetween ports
•Fully asynchronous operation from either port•TTL-compatible, single 5V (±10%) power supply•Available in 84-pin PGA and 84-pin PLCC
•Industrial temperature range (–40°C to +85°C) is avail-able, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
R/WLUBLR/WRUBRLBLCELOELLBRCEROERI/O8L-I/O15LI/O0L-I/O7LBUSYL(1,2)I/OControlI/OControlI/O8R-I/O15RI/O0R-I/O7RBUSYR(1,2)A13LA0LAddressDecoder14MEMORYARRAY14AddressDecoderA13RA0RCELARBITRATIONSEMAPHORELOGICCERSEMLM/SSEMR2939 drw 01NOTES:
1.(MASTER): BUSY is output; (SLAVE): BUSY is input.2.BUSY outputs are non-tri-stated push-pull.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC 2939/3
6.17
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IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DESCRIPTION:
The IDT7026 is a high-speed 16K x 16 Dual-Port StaticRAM. The IDT7026 is designed to be used as a stand-aloneDual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word systems. Using the IDTMASTER/SLAVE Dual-Port RAM approach in 32-bit or widermemory system applications results in full-speed, error-freeoperation without the need for additional discrete logic.
This device provides two independent ports with separatecontrol, address, and I/O pins that permit independent,asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by CEpermits the on-chip circuitry of each port to enter a very lowstandby power mode.
Fabricated using IDT’s CMOS high-performance technol-ogy, these devices typically operate on only 750mW of power.The IDT7026 is packaged in a ceramic 84-pin PGA, and a84-pin PLCC. Military grade product is manufactured in com-pliance with the latest revision of MIL-STD-883, Class B,making it ideally suited to military temperature applicationsdemanding the highest level of performance and reliability.
PIN CONFIGURATIONS (1,2)
I/O4LI/O3LI/O2LI/O0LOELR/WLSEMLCELI/O5LI/O7LI/O6LGNDI/O1LA13LA12LA11LA10LVCCUBLLBLINDEXI/O8LI/O9LI/O10LI/O11LI/O12LI/O13LGNDI/O14LI/O15LVCCGNDI/O0RI/O1RI/O2RVCCI/O3RI/O4RI/O5RI/O6RI/O7RI/O8R111098765432184838281807978777675741213141516171819202122232425262728293031IDT7026J84-184-PIN PLCCTOP VIEW(3)73727170696867666564636261605958575655A9LA8LA7LA6LA5LA4LA3LA2LA1LA0LBUSYLGNDM/SBUSYRA0RA1RA2RA3RA4RA5RA6RA7R2939 drw 025432333435363738394041424344454647484950515253I/O11RI/O15RI/O12RI/O13RI/O14RGNDCERR/WRGNDLBRA13RA12RA11RI/O9RI/O10RSEMRA10ROERUBRA9RA8RNOTES:
1. All Vcc pins must be connected to the power supply.2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the actual part-marking.
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IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONT'D) (1,2)
636160585554514846454211I/O7L66I/O5L64I/O4L62I/O2L59I/O0L56OEL49SEML50LBL47A12L44A11L43A8L4010I/O10L67I/O8L65I/O6LI/O3LI/O1L57UBL53CEL52A13LA10LA9L41A6L3909I/O11L69I/O9L68GNDVCCR/WLA7L38A5L3708I/O13L72I/O12L717333A4L35A3L3407I/O15L75I/O14L70VCC74IDT7026G84-384-PIN PGATOP VIEW(3)
BUSYL32A1L31A0L3606I/O0R76GND77GND78GND28M/S29A2L3005I/O1R79I/O2R80VCCA1RA0R26BUSYR2704I/O3R81I/O4R8371112A3R23A2R2503I/O5R821I/O7R25GND8GND10SEMR141720A6R22A4R2402I/O6R843I/O9RI/O10R4I/O13R6I/O15R9R/WR15UBR13A12R16A9R18A7R19A5R2101I/O8RAI/O11RBI/O12RCI/O14RDOERELBRFCERGA13RHA11RJA10RKA8RL2939 drw 03
IndexNOTES:
1.All VCC pins must be connected to power supply.2.All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
PIN NAMES
Left PortCELR/WLOELA0L – A13LI/O0L – I/O15LSEMLUBLLBLBUSYL
M/SVCCGND
Right PortCERR/WROERA0R – A13RI/O0R – I/O15RSEMRUBRLBRBUSYR
Names
Chip EnableRead/Write EnableOutput EnableAddress
Data Input/OutputSemaphore EnableUpper Byte SelectLower Byte SelectBusy Flag
Master or Slave SelectPowerGround
2939 tbl 01
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GradeMilitaryCommercial
AmbientTemperature–55°C to +125°C0°C to +70°C
GND0V0V
VCC5.0V ± 10%5.0V ± 10%
2939 tbl 02
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IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL
Inputs(1)CEHXLLLLLLX
R/WXXLLLHHHX
OEXXXXXLLLH
UBXHLHLLHLX
LBXHHLLHLLX
SEMHHHHHHHHX
OutputsI/O8-15High-ZHigh-ZDATAINHigh-ZDATAINDATAOUTHigh-ZHigh-Z
I/O0-7High-ZHigh-ZHigh-ZDATAINDATAINHigh-Z
Both Bytes DeselectedWrite to Upper Byte OnlyWrite to Lower Byte OnlyWrite to Both BytesRead Upper Byte Only
Mode
Deselected: Power-Down
DATAOUTRead Lower Byte OnlyHigh-Z
Outputs Disabled
2939 tbl 03
DATAOUTDATAOUTRead Both Bytes
NOTE:
1.A0L — A13L ≠ A0R — A13R.
TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL(1)
InputsCEHXHXLLXXR/WHHOELLXXXXUBXHXHLXLBXHXHXLSEMLLLLLLOutputsI/O8-15I/O0-7ModeDATAOUTDATAOUTRead Data in Semaphore FlagDATAOUTDATAOUTRead Data in Semaphore FlagDATAINDATAIN——DATAINDATAIN——Write I/O0 into Semaphore FlagWrite I/O0 into Semaphore FlagNot AllowedNot Allowed2939 tbl 04
NOTE:1.There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2.
ABSOLUTE MAXIMUM RATINGS(1)
SymbolVTERM(2)
Rating
Commercial
Military–0.5 to +7.0
UnitV
Terminal Voltage–0.5 to +7.0with Respectto GNDOperatingTemperatureTemperatureUnder BiasStorage
TemperatureDC OutputCurrent
0 to +70–55 to +125–55 to +125
50
RECOMMENDED DC OPERATINGCONDTIONS
SymbolVCCGNDVIHVIL
ParameterSupply VoltageSupply VoltageInput High VoltageInput Low Voltage
Min.4.502.2–0.5(1)
Typ.5.00——
Max.Unit5.506.0(2)0.8
VVVV
2939 tbl 06
TATBIASTSTGIOUT
–55 to +125–65 to +135–65 to +150
50
°C°C°CmA
NOTES:
1.VIL > -1.5V for pulse width less than 10ns.2.VTERM must not exceed Vcc + 0.5V.
NOTES:2939 tbl 051.Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stressrating only and functional operation of the device at these or any otherconditions above those indicated in the operational sections of thisspecification is not implied. Exposure to absolute maximum ratingconditions for extended periods may affect reliability.
2.VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc+ 0.5V.
CAPACITANCE(1) (TA = +25°C, f = 1.0MHz)
SymbolCINCOUT
ParameterInput CapacitanceOutput
Capacitance
Conditions(2)Max.VIN = 3dvVOUT = 3dv
910
UnitpFpF
NOTES:2939 tbl 071.This parameter is determined by device characterization but is not
production tested.
2.3dV represents the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
4
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HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)
IDT7026S
Symbol|ILI||ILO|VOLVOH
Parameter
Input Leakage Current(1)Output Leakage CurrentOutput Low VoltageOutput High Voltage
Test ConditionsVCC = 5.5V, VIN = 0V to VCCCE = VIH, VOUT = 0V to VCCIOL = 4mAIOH = –4mA
Min.———2.4
Max.10100.4—
IDT7026LMin.———2.4
Max.550.4—
UnitµAµAVV
2939 tbl 08
NOTE:
1.At Vcc = 2.0V, input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 5.0V ± 10%)
SymbolICC
Parameter
Dynamic OperatingCurrent
(Both Ports Active)
ISB1
Standby Current(Both Ports — TTLLevel Inputs)
ISB2
Standby Current(One Port — TTLLevel Inputs)
ISB3
Full Standby Current(Both Ports — AllCMOS Level Inputs)
TestCondition
CE = VIL, Outputs OpenSEM = VIHf = fMAX(3)
CER = CEL = VIHSEMR = SEML = VIHf = fMAX(3)
CE\"A\" = VIL and CE\"B\" = VIH(5)Active Port Outputs Open,f = fMAX(3)
SEMR = SEML = VIHBoth Ports CEL andCER > VCC - 0.2V
VIN > VCC - 0.2V orVIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2VCE\"A\" < 0.2V andCE\"B\" > VCC - 0.2V(5)
SEMR = SEML > VCC - 0.2VVIN > VCC - 0.2V orVIN < 0.2VActive Port Outputs Open,f = fMAX(3)
VersionMIL.COM’L.MIL.COM’L.MIL.COM’L.MIL.COM’L.
SLSLSLSLSLSLSLSLSLSL
7026X207026X25Com'l. Only
Typ.(2)Max.Typ.(2)Max.Unit——180180——3030——115115——1.00.2——110110
——315275——8560——210180——155——185160
170170170170252525251051051051051.00.21.00.2100100100100
3453053052651008085602302002001703010155200175170145
mAmAmAmAmA
ISB4
Full Standby Current(One Port — All
CMOS Level Inputs)
MIL.
COM’L.
NOTES:2939 tbl 091.\"X\" in part numbers indicates power rating (S or L).
2.VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
3.At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / tRC, and using “AC Test Conditions”
of input levels of GND to 3V.
4.f = 0 means no address or control lines change.
5.Port \"A\" may be either left or right port. Port \"B\" is the opposite from port \"A\".
6.175
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IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)(Con't.) (VCC = 5.0V ± 10%)
7026X35
SymbolICC
Parameter
Dynamic OperatingCurrent
(Both Ports Active)
ISB1
Standby Current(Both Ports — TTLLevel Inputs)
ISB2
Standby Current(One Port — TTLLevel Inputs)
ISB3
Full Standby Current(Both Ports — AllCMOS Level Inputs)
TestCondition
CE = VIL, Outputs OpenSEM = VIHf = fMAX(3)
CEL = CER = VIHSEMR = SEML = VIHf = fMAX(3)
CE\"A\"=VIL and CE\"B\"=VIH(5)Active Port Outputs Open,f = fMAX(3)
SEMR = SEML = VIHBoth Ports CEL andCER > VCC - 0.2V
VIN > VCC - 0.2V orVIN < 0.2V, f = 0(4)
SEMR = SEML >VCC - 0.2VCE\"A\" < 0.2V andCE\"B\" > VCC - 0.2V(5)
SEMR = SEML >VCC - 0.2VVIN > VCC - 0.2V orVIN < 0.2VActive Port Outputs Open,f = fMAX(3)
VersionMIL.COM’L.MIL.COM’L.MIL.COM’L.MIL.COM’L.
SLSLSLSLSLSLSLSLSLSL
7026X55
Typ.(2)Max.Typ.(2)Max.Unit16016016016020202020959595951.00.21.00.290909090
3352952952551008085602151851851553010155190165160135
15015015015013131313858585851.00.21.00.280808080
3102702702301008085601951651651353010155175150135110
mAmAmAmAmA
ISB4
Full Standby Current(One Port — All
CMOS Level Inputs)
MIL.
COM’L.mA
NOTES:
1. \"X\" in part numbers indicates power rating (S or L).
2.VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
3.At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using
“AC Test Conditions” of input levels of GND to 3V.4.f = 0 means no address or control lines change.
5.Port \"A\" may be either left or right port. Port \"B\" is the opposite from port \"A\".
2939 tbl 10
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IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
5VAC TEST CONDITIONS
Input Pulse LevelsInput Rise/Fall Times
Input Timing Reference LevelsOutput Reference LevelsOutput Load
GND to 3.0V5ns Max.1.5V1.5VFigures 1 and 2
2939 tbl 11
5V893Ω893ΩDATAOUTDATAOUTBUSYINT347Ω30pF347Ω5pF2939 drw 042939 drw 05Figure 1. AC Output Load
Figure 2. Output Test Load (for tLZ, tHZ, tWZ, tOW) * Including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
SymbolREAD CYCLEtRCtAAtACEtABEtAOEtOHtLZtHZtPUtPDtSOPtSAA
Read Cycle TimeAddress Access TimeChip Enable Access Time(3)Byte Enable Access Time(3)Output Enable Access TimeOutput Hold from Address ChangeOutput Low-Z Time(1, 2)Output High-Z Time(1, 2)
Chip Enable to Power Up Time(2)Chip Disable to Power Down TimeSemaphore Address Access Time
(2)
Parameter
IDT7026X20Com'l. OnlyMin.Max.20————33—0—10—
—20202012——12—20—20
IDT7026X25Min.25————33—0—12—
Max.—25252513——15—25—25
Unitnsnsnsnsnsnsnsnsnsnsnsns
Semaphore Flag Update Pulse (OE or SEM)
IDT7026X35
SymbolREAD CYCLEtRCtAAtACEtABEtAOEtOHtLZtHZtPUtPDtSOPtSAA
Read Cycle TimeAddress Access TimeChip Enable Access Time(3)Byte Enable Access Time(3)Output Enable Access TimeOutput Hold from Address ChangeOutput Low-Z Time(1, 2)Output High-Z Time(1, 2)
Chip Enable to Power Up Time(2)Chip Disable to Power Down Time(2)
Semaphore Flag Update Pulse (OE or SEM)Semaphore Address Access Time
35————33—0—15—
—35353520——15—35—35
Parameter
Min.
Max.
IDT7026X55Min.55————33—0—15—
Max.—55555530——25—50—55
Unitnsnsnsnsnsnsnsnsnsnsnsns
2939 tbl 12
NOTES:
1.Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).2.This parameter is guaranteed by device characterization, but is not production tested.
3.To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.4.\"X\" in part numbers indicates power rating (S or L).
6.17
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IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
tRCADDRtAA(4)(4)tACEtAOEOEtABEUB, LB(4)(4)CER/WtLZ(1)DATAOUTVALID DATAtOH(4)tHZ(2)BUSYOUTtBDD(3, 4)2939 drw 06NOTES:
1.Timing depends on which signal is asserted last, OE, CE, LB, or UB.2.Timing depends on which signal is de-asserted first CE, OE, LB, or UB.
3.tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operationsBUSY has no relation to valid output data.
4.Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.5.SEM = VIH.
TIMING OF POWER-UP POWER-DOWN
CEICCISBtPU50%tPD50%2939 drw 076.178
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IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE (5)
SymbolWRITE CYCLEtWCtEWtAWtAStWPtWRtDWtHZtDHtWZtOWtSWRDtSPS
Write Cycle Time
Chip Enable to End-of-Write(3)Address Valid to End-of-WriteAddress Set-up Time(3)Write Pulse WidthWrite Recovery TimeData Valid to End-of-WriteOutput High-Z Time(1, 2)Data Hold Time(4)
Write Enable to Output in High-ZSEM Flag Write to Read TimeSEM Flag Contention Window
(1, 2)
Parameter
IDT7026X20Com'l. OnlyMin.Max.201515015015—0—055
———————12—12———
IDT7026X25Min.252020020015—0—055
Max.———————15—15———
Unitnsnsnsnsnsnsnsnsnsnsnsnsns
Output Active from End-of-Write(1, 2, 4)IDT7026X35
SymbolWRITE CYCLEtWCtEWtAWtAStWPtWRtDWtHZtDHtWZtOWtSWRDtSPS
Write Cycle Time
Chip Enable to End-of-Write(3)Address Valid to End-of-WriteAddress Set-up Time(3)Write Pulse WidthWrite Recovery TimeData Valid to End-of-WriteOutput High-Z Time(1, 2)Data Hold Time(4)
Write Enable to Output in High-Z(1, 2)Output Active from End-of-Write(1, 2, 4)SEM Flag Write to Read TimeSEM Flag Contention Window
353030025015—0—055
———————15—15———
Parameter
Min.
Max.
IDT7026X55Min.554545040030—0—055
Max.———————25—25———
Unitnsnsnsnsnsnsnsnsnsnsnsnsns
NOTES:2939 tbl 13
1.Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).2.This parameter is guaranteed by device characterization, but is not production tested.
3.To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.4.The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary
over voltage and temperature, the actual tDH will always be smaller than the actual tOW.5.\"X\" in part numbers indicates power rating (S or L).
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IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1,5,8)
tWCADDRESStHZOEtAWCE or SEM(9)(7)UB or LB(9)tAS(6)R/WtWZ(7)DATAOUT(4)tWP(2)tWR(3)tOW(4)tDWDATAINtDH2939 drw 08TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE, UB, LB CONTROLLED TIMING(1,5)
tWCADDRESStAWCE or SEM(9)tASUB or LB(9)(6)tEW(2)tWR(3)R/WtDWDATAIN2939 drw 09tDHNOTES:
1.R/W or CE or UB and LB must be HIGH during all address transitions.
2.A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.3.tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.4.During this period, the I/O pins are in the output state and input signals must not be applied.
5.If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.6.Timing depends on which enable signal is asserted last, CE or R/W.
7.This parameter is guaranteed by device characterization, but is not production tested. Transition is measured + 200mV from steady state with the OutputTest Load (Figure 2).
8.If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and datato be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse canbe as short as the specified tWP.
9.To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.1710
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IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
tSAAA0-A2
VALID ADDRESStWRtAWtEWtDWDATAINVALIDtASR/W
tSWRDOE
Write CycleRead Cycle2939 drw 10tOHVALID ADDRESStACEtSOPDATAOUTVALID(2)SEM
I/O0
tWPtDHtAOENOTES:
1.CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle).2. \"DATAOUT VALID\" represents all I/O's (I/O0-I/O15) equal to the semaphore value.
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
A0\"A\"-A2\"A\"MATCHSIDE(2)“A”R/W\"A\"SEM\"A\"tSPSA0\"B\"-A2\"B\"(2)MATCHSIDE“B”R/W\"B\"SEM\"B\"2939 drw 11NOTES:
1.DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.
2.All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.3.This parameter is measured from R/W\"A\" or SEM\"A\" going HIGH to R/W\"B\" or SEM\"B\" going HIGH.4.If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
6.1711
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IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
Symbol
BUSY TIMING (M/S = VIH)tBAAtBDAtBACtBDCtAPStBDDtWHtWBtWHtWDDtDDD
BUSY Access Time from Address MatchBUSY Disable Time from Address Not MatchedBUSY Access Time from Chip Enable LowBUSY Disable Time from Chip Enable HighArbitration Priority Set-up Time(2)BUSY Disable to Valid Data(3)Write Hold After BUSY(5)BUSY Input to Write(4)Write Hold After BUSY
(5)
Parameter
IDT7026X20Com'l. OnlyMin.Max.————5—15015——
20202017—30———4530
IDT7026X25Min.————5—17017——
Max.20202017—30———5035
Unitnsnsnsnsnsnsnsnsnsnsns
BUSY TIMING (M/S = VIL)
PORT-TO-PORT DELAY TIMING
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)IDT7026X35
Symbol
BUSY TIMING (M/S = VIH)tBAAtBDAtBACtBDCtAPStBDDtWH
BUSY Access Time from Address MatchBUSY Disable Time from Address Not MatchedBUSY Access Time from Chip Enable LowBUSY Disable Time from Chip Enable HighArbitration Priority Set-up Time(2)BUSY Disable to Valid DataWrite Hold After BUSY(5)BUSY Input to Write(4)Write Hold After BUSY(5)Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
(3)
IDT7026X55Min.————5—25
Max.45404035—40—
Unitnsnsnsnsnsnsns
ParameterMin.————5—25
Max.20202020—35—
BUSY TIMING (M/S = VIL)tWBtWHtWDDtDDD
025——
——6045
025——
——8065
nsnsnsns
PORT-TO-PORT DELAY TIMING
NOTES:2939 tbl 15
1.Port-to-port delay through RAM cells from writing port to reading port, refer to \"Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)\".2.To ensure that the earlier of the two ports wins.
3.tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).4.To ensure that the write cycle is inhibited on port \"B\" during contention on port \"A\".5.To ensure that a write cycle is completed on port \"B\" after contention on port \"A\".6.\"X\" in part numbers indicates power rating (S or L).
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TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY (M/S = VIH)(2,4,5)
tWCADDR\"A\"MATCHtWPR/W\"A\"tDWDATAIN \"A\"tAPS(1)ADDR\"B\"tBAABUSY\"B\"tWDDDATAOUT \"B\"NOTES:
1.To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).2.CEL = CER = VIL.
3.OE = VIL for the reading port.
4.If M/S = VIL (slave), BUSY is an input. Then for this example BUSY\"A\" = VIH and BUSY\"B\" input is shown above.
5.All timing is the same for left and right ports. Port \"A\" may be either the left or right port. Port \"B\" is the port opposite from port \"A\".
VALIDtDHVALIDMATCHtBDAtBDDtDDD(3)2939 drw 12TIMING WAVEFORM OF WRITE WITH BUSY (M/S = VIL)
tWPR/W\"A\"tWB(3)BUSY\"B\"tWH(1)R/W\"B\"(2)2939 drw 13NOTES:
1.tWH must be met for both BUSY input (SLAVE) and output (MASTER).2.BUSY is asserted on port \"B\" blocking R/W\"B\", until BUSY\"B\" goes High.
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WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING (M/S = VIH)(1)
ADDR\"A\"and \"B\"ADDRESSES MATCHCE\"A\"tAPS(2)CE\"B\"tBACBUSY\"B\"tBDC2939 drw 15WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING(M/S = VIH)(1)
ADDR\"A\"tAPS(2)ADDR\"B\"MATCHING ADDRESS \"N\"tBAABUSY\"B\"tBDA2939 drw 15ADDRESS \"N\"NOTES:
1.All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2.If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
TRUTH TABLE III — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1,2)
Functions
No Action
Left Port Writes \"0\" to SemaphoreRight Port Writes \"0\" to SemaphoreLeft Port Writes \"1\" to SemaphoreLeft Port Writes \"0\" to SemaphoreRight Port Writes \"1\" to SemaphoreLeft Port Writes \"1\" to SemaphoreRight Port Writes \"0\" to SemaphoreRight Port Writes \"1\" to SemaphoreLeft Port Writes \"0\" to SemaphoreLeft Port Writes \"1\" to Semaphore
D0 - D15 Left
10011011101
D0 - D15 Right
11100110111
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphoreRight port obtains semaphore token
No change. Left port has no write access to semaphoreLeft port obtains semaphore tokenSemaphore free
Right port has semaphore tokenSemaphore free
Left port has semaphore tokenSemaphore free
2683 tbl 16
Status
NOTES:
1.This table denotes a sequence of events for only one of the eight semaphores on the IDT7026.
2.There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2.
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TRUTH TABLE IV —
ADDRESS BUSY ARBITRATION
Inputs
CELXHXL
CERXXHL
A0L-A13LA0R-A13R
NO MATCHMATCHMATCHMATCH
WIDTH EXPANSION WITH BUSY LOGICMASTER/SLAVE ARRAYS
FunctionNormalNormalNormalWrite Inhibit(3)
OutputsBUSYL(1)BUSYR(1)
HHH(2)
HHH(2)
NOTES:2683 tbl 171.Pins BUSYL and BUSYR are both outputs when the part is configured as
a master. Both are inputs when configured as a slave. BUSYX outputs onthe IDT7026 are push pull, not open drain outputs. On slaves the BUSYXinput internally inhibits writes.
2.LOW if the inputs to the opposite port were stable prior to the address and
enable inputs of this port. HIGH if the inputs to the opposite port becamestable after the address and enable inputs of this port. If tAPS is not met,either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputscannot be LOW simultaneously.
3.Writes to the left port are internally ignored when BUSYL outputs are
driving LOW regardless of actual logic level on the pin. Writes to the rightport are internally ignored when BUSYR outputs are driving LOW regard-less of actual logic level on the pin.
When expanding an IDT7026 RAM array in width whileusing busy logic, one master part is used to decide which sideof the RAM array will receive a busy indication, and to outputthat indication. Any number of slaves to be addressed in thesame address range as the master, use the busy signal as awrite inhibit signal. Thus on the IDT7026 RAM the busy pin isan output if the part is used as a master (M/S pin = H), and thebusy pin is an input if the part used as a slave (M/S pin = L) asshown in Figure 3.
DECODERMASTERDual PortRAMBUSYLCEBUSYRSLAVEDual PortRAMBUSYLCEBUSYRBUSYLMASTERDual PortRAMBUSYLCEBUSYRSLAVEDual PortRAMBUSYLCEBUSYRBUSYR2939 drw 16FUNCTIONAL DESCRIPTION
The IDT7026 provides two ports with separate control,address and I/O pins that permit independent access for readsor writes to any location in memory. The IDT7026 has anautomatic power down feature controlled by CE. The CEcontrols on-chip power down circuitry that permits therespective port to go into a standby mode when not selected(CE HIGH). When a port is enabled, access to the entirememory array is permitted.
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7026 RAMs.
BUSY LOGIC
Busy Logic provides a hardware indication that both portsof the RAM have accessed the same location at the sametime. It also allows one of the two accesses to proceed andsignals the other side that the RAM is “Busy”. The busy pin canthen be used to stall the access until the operation on the otherside is completed. If a write operation has been attemptedfrom the side that receives a busy indication, the write signalis gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for allapplications. In some cases it may be useful to logically ORthe busy outputs together and use any busy indication as aninterrupt source to flag the event of an illegal or illogicaloperation. If the write inhibit function of busy logic is notdesirable, the busy logic can be disabled by placing the partin slave mode with the M/S pin. Once in slave mode the BUSYpin operates solely as a write inhibit input pin. Normal opera-tion can be programmed by tying the BUSY pins HIGH. Ifdesired, unintended write operations can be prevented to aport by tying the busy pin for that port LOW.
The busy outputs on the IDT 7026 RAM in master mode,are push-pull type outputs and do not require pull up resistorsto operate. If these RAMs are being expanded in depth, thenthe busy indication for the resulting array requires the use ofan external AND gate.
If two or more master parts were used when expanding inwidth, a split decision could result with one master indicatingbusy on one side of the array and another master indicatingbusy on one other side of the array. This would inhibit the writeoperations from one port for part of a word and inhibit the writeoperations from the other port for the other part of the word.The busy arbitration, on a master, is based on the chipenable and address signals only. It ignores whether an accessis a read or write. In a master/slave array, both address andchip enable must be valid long enough for a busy flag to beoutput from the master before the actual write pulse can beinitiated with either the R/W signal or the byte enables. Failureto observe this timing can result in a glitched internal writeinhibit signal and corrupted data in the slave.
SEMAPHORES
The IDT7026 is an extremely fast Dual-Port 16K x 16CMOS Static RAM with an additional 8 address locationsdedicated to binary semaphore flags. These flags allow eitherprocessor on the left or right side of the Dual-Port RAM to claima privilege over the other processor for functions defined bythe system designer’s software. As an example, the sema-phore can be used by one processor to inhibit the other fromaccessing a portion of the Dual-Port RAM or any other sharedresource.
The Dual-Port RAM features a fast access time, and bothports are completely independent of each other. This meansthat the activity on the left port in no way slows the access timeof the right port. Both ports are identical in function to standard
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CMOS Static RAM and can be read from, or written to, at thesame time with the only possible conflict arising from thesimultaneous writing of, or a simultaneous READ/WRITE of,a non-semaphore location. Semaphores are protected againstsuch ambiguous situations and may be used by the systemprogram to avoid any conflicts in the non-semaphore portionof the Dual-Port RAM. These devices have an automaticpower-down feature controlled by CE, the Dual-Port RAMenable, and SEM, the semaphore enable. The CE and SEMpins control on-chip power down circuitry that permits therespective port to go into standby mode when not selected.This is the condition which is shown in Truth Table where CEand SEM are both HIGH.
Systems which can best use the IDT7026 contain multipleprocessors or controllers and are typically very high-speedsystems which are software controlled or software intensive.These systems can benefit from a performance increaseoffered by the IDT7026's hardware semaphores, which pro-vide a lockout mechanism without requiring complex pro-gramming.
Software handshaking between processors offers themaximum in system flexibility by permitting shared resourcesto be allocated in varying configurations. The IDT7026 doesnot use its semaphore flags to control any resources throughhardware, thus allowing the system designer total flexibility insystem architecture.
An advantage of using semaphores rather than the morecommon methods of hardware arbitration is that wait statesare never incurred in either processor. This can prove to bea major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which areindependent of the Dual-Port RAM. These latches can beused to pass a flag, or token, from one port to the other toindicate that a shared resource is in use. The semaphoresprovide a hardware assist for a use assignment method called“Token Passing Allocation.” In this method, the state of asemaphore latch is used as a token indicating that sharedresource is in use. If the left processor wants to use thisresource, it requests the token by setting the latch. Thisprocessor then verifies its success in setting the latch byreading it. If it was successful, it proceeds to assume controlover the shared resource. If it was not successful in setting thelatch, it determines that the right side processor has set thelatch first, has the token and is using the shared resource. Theleft processor can then either repeatedly request thatsemaphore’s status or remove its request for that semaphoreto perform another task and occasionally attempt again togain control of the token via the set and test sequence. Oncethe right side has relinquished the token, the left side shouldsucceed in gaining control.
The semaphore flags are active LOW. A token is re-quested by writing a zero into a semaphore latch and isreleased when the same side writes a one to that latch.The eight semaphore flags reside within the IDT7026 in aseparate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the SEMpin (which acts as a chip select for the semaphore flags) andusing the other control pins (Address, OE, and R/W) as theywould be used in accessing a standard Static RAM. Each ofthe flags has a unique address which can be accessed byeither side through address pins A0 – A2. When accessing thesemaphores, none of the other address pins has any effect.When writing to a semaphore, only data pin D0 is used. Ifa low level is written into an unused semaphore location, thatflag will be set to a zero on that side and a one on the other side(see Table III). That semaphore can now only be modified bythe side showing the zero. When a one is written into the samelocation from the same side, the flag will be set to a one for bothsides (unless a semaphore request from the other side ispending) and then can be written to by both sides. The fact thatthe side which is able to write a zero into a semaphoresubsequently locks out writes from the other side is whatmakes semaphore flags useful in interprocessor communica-tions. (A thorough discussing on the use of this feature followsshortly.) A zero written into the same location from the otherside will be stored in the semaphore request latch for that sideuntil the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into alldata bits so that a flag that is a one reads as a one in all databits and a flag containing a zero reads as all zeros. The readvalue is latched into one side’s output register when that side'ssemaphore select (SEM) and output enable (OE) signals goactive. This serves to disallow the semaphore from changingstate in the middle of a read cycle due to a write cycle from theother side. Because of this latch, a repeated read of asemaphore in a test loop must cause either signal (SEM or OE)to go inactive or the output will never change.
A sequence WRITE/READ must be used by the sema-phore in order to guarantee that no system level contentionwill occur. A processor requests access to shared resourcesby attempting to write a zero into a semaphore location. If thesemaphore is already in use, the semaphore request latch willcontain a zero, yet the semaphore flag will appear as one, afact which the processor will verify by the subsequent read(see Table III). As an example, assume a processor writes azero to the left port at a free semaphore location. On asubsequent read, the processor will verify that it has writtensuccessfully to that location and will assume control over theresource in question. Meanwhile, if a processor on the rightside attempts to write a zero to the same semaphore flag it willfail, as will be verified by the fact that a one will be read fromthat semaphore on the right side during subsequent read.Had a sequence of READ/WRITE been used instead, systemcontention problems could have occurred during the gapbetween the read and write cycles.
It is important to note that a failed semaphore request mustbe followed by either repeated reads or by writing a one intothe same location. The reason for this is easily understood bylooking at the simple logic diagram of the semaphore flag inFigure 4. Two semaphore request latches feed into a sema-phore flag. Whichever latch is first to present a zero to thesemaphore flag will force its side of the semaphore flag LOWand the other side HIGH. This condition will continue until a
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L PORTSEMAPHOREREQUEST FLIP FLOPD0WRITESEMAPHOREREADDQR PORTSEMAPHOREREQUEST FLIP FLOPQDD0WRITESEMAPHOREREADFigure 4. IDT7026 Semaphore Logic
2939 drw 17one is written to the same semaphore request latch. Shouldthe other side’s semaphore request latch have been written toa zero in the meantime, the semaphore flag will flip over to theother side as soon as a one is written into the first side’srequest latch. The second side’s flag will now stay LOW untilits semaphore request latch is written to a one. From this it iseasy to understand that, if a semaphore is requested and theprocessor which requested it no longer needs the resource,the entire system can hang up until a one is written into thatsemaphore request latch.
The critical case of semaphore timing is when both sidesrequest a single token by attempting to write a zero into it atthe same time. The semaphore logic is specially designed toresolve this problem. If simultaneous requests are made, thelogic guarantees that only one side receives the token. If oneside is earlier than the other in making the request, the firstside to make the request will receive the token. If bothrequests arrive at the same time, the assignment will bearbitrarily made to one port or the other.
One caution that should be noted when using semaphoresis that semaphores alone do not guarantee that access to aresource is secure. As with any powerful programmingtechnique, if semaphores are misused or misinterpreted, asoftware error can easily happen.
Initialization of the semaphores is not automatic and mustbe handled via the initialization program at power-up. Sinceany semaphore request flag which contains a zero must bereset to a one, all semaphores on both sides should have aone written into them at initialization from both sides to assurethat they will be free when needed.
USING SEMAPHORES—SOME EXAMPLES
Perhaps the simplest application of semaphores is theirapplication as resource markers for the IDT7026’s Dual-PortRAM. Say the 16K x 16 RAM was to be divided into two 8Kx 16 blocks which were to be dedicated at any one time toservicing either the left or right port. Semaphore 0 could beused to indicate the side which would control the lower sectionof memory, and Semaphore 1 could be defined as theindicator for the upper section of memory.
To take a resource, in this example the lower 8K of
Dual-Port RAM, the processor on the left port could write andthen read a zero in to Semaphore 0. If this task were success-fully completed (a zero was read back rather than a one), theleft processor would assume control of the lower 8K. Mean-while the right processor was attempting to gain control of theresource after the left processor, it would read back a one inresponse to the zero it had attempted to write into Semaphore0. At this point, the software could choose to try and gaincontrol of the second 8K section by writing, then reading a zerointo Semaphore 1. If it succeeded in gaining control, it wouldlock out the left side.
Once the left side was finished with its task, it would writea one to Semaphore 0 and may then try to gain access toSemaphore 1. If Semaphore 1 was still occupied by the rightside, the left side could undo its semaphore request andperform other tasks until it was able to write, then read a zerointo Semaphore 1. If the right processor performs a similartask with Semaphore 0, this protocol would allow the twoprocessors to swap 8K blocks of Dual-Port RAM with eachother.
The blocks do not have to be any particular size and caneven be variable, depending upon the complexity of thesoftware using the semaphore flags. All eight semaphorescould be used to divide the Dual-Port RAM or other sharedresources into eight parts. Semaphores can even be assigneddifferent meanings on different sides rather than being givena common meaning as was shown in the example above.Semaphores are a useful form of arbitration in systems likedisk interfaces where the CPU must be locked out of a sectionof memory during a transfer and the I/O device cannot tolerateany wait states. With the use of semaphores, once the twodevices has determined which memory area was “off-limits” tothe CPU, both the CPU and the I/O devices could access theirassigned portions of memory continuously without any waitstates.
Semaphores are also useful in applications where nomemory “WAIT” state is available on one or both sides. Oncea semaphore handshake has been performed, both proces-sors can access their assigned RAM segments at full speed.Another application is in the area of complex data struc-tures. In this case, block arbitration is very important. For thisapplication one processor may be responsible for building andupdating a data structure. The other processor then reads andinterprets that data structure. If the interpreting processorreads an incomplete data structure, a major error conditionmay exist. Therefore, some sort of arbitration must be usedbetween the two different processors. The building processorarbitrates for the block, locks it and then is able to go in andupdate the data structure. When the update is completed, thedata structure block is released. This allows the interpretingprocessor to come back and read the complete data structure,thereby guaranteeing a consistent data structure.
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ORDERING INFORMATION
IDTXXXXXDeviceTypeAPower999SpeedAPackageAProcess/TemperatureRangeBlankBCommercial (0°C to +70°C)Military (–55°C to +125°C) Compliant to MIL-STD-883, Class B84-pin PGA (G84-3)84-pin PLCC (J84-1)GJ20253555Commercial OnlySpeed in nanosecondsSL7026Standard PowerLow Power256K (16K x 16) Dual-PortRAM2939 drw 186.1718
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