Letters
ALab-ScaleAlternativeInterconnectionSolutionofSemiconductorDice
CompatiblewithPowerModules3-DIntegration
LudovicM´enager,MaherSoueidan,BrunoAllard,VincentBley,andBenoˆıtSchlegel
Abstract—Increaseinthepowerdensityofpowermodulesre-quiresaninterconnectiontechnologyalternativetowire-bonding
technology.Emerginginterconnectiontechnologiesallowa3-Dpackagingofpowermodules.Aproposalofinterconnectionso-lutionforthepowersemiconductordiceispresentedhere;itisbasedoncoppermicropoststhatareelectroplatedontopsideofthedie.Thediewithitsmicropostsisthenattachedtoatopdirect-bondingcopper(DBC)substrateusingacopper/tintran-sientliquidphasetechnique.TheassemblyofthebacksideofthedietoabottomDBCsubstrateisprocessedconcurrentlyusingthesametransientliquidphasetechnique.Thebenefitsorlimitationsofthesubstrateontheassemblyarenotdiscussedinthisletter.Manufacturingandelectricalcharacterizationofapowersemi-conductordiewiththemicropostsinterconnectionispresentedindetail.
IndexTerms—3-Dpackaging,Electroplating,powerdensity,semiconductordie,transientliquidphasebonding.
I.INTRODUCTION
T
HEMOSTcommondie-levelinterconnecttechnologyinpowermodulesiswirebonding.Maturity,flexibility,andlowcostaremainfactorsthatexplaintheuseofthewire-bondingtechnologyplusrecentimprovementwithrespecttotin-lesssol-derregulationorhightemperaturecapability.However,wire-bondingtechnologyhaselectricalandthermomechanicallim-itations.Awireusuallyinvolvesaparasiticinductanceabout10nH[1].Thisparasiticinductanceinducesovervoltagesattheswitchlevelandisgloballyalimitingfactorregardingthemaximumswitchingfrequency.ItslowsdowntheturnON/OFFoftheswitchthatinducesanincreaseincommutationlosses.Italsocontributestothedynamiccurrentunbalancinginparallel-connecteddice[1].Fromathermalpointofview,theheatfluxdissipationislimitedtoonedirection.Infact,themainther-malpathisthebacksideofthedice.Finally,wirebondsare
ManuscriptreceivedOctober8,2009;revisedNovember27,2009.DateofcurrentversionJune18,2010.RecommendedforpublicationbyAssociateEditorK.Sheng.L.M´enageriswiththeINRETS,LTNLaboratory,VersaillesF-78008,France(e-mail:ludovic.menager@inrets.fr).
M.SoueidanandB.AllardarewiththeAmpereLaboratory,InstitutNa-tionaldesSciencesAppliqu´ees(INSA)Lyon,Universit´edeLyon,CNRSUMR5005,VilleurbanneF-69621,France(e-mail:maher.soueidan@insa-lyon.fr;bruno.allard@insa-lyon.fr).
V.BleyandB.SchlegelarewiththeLaplaceLaboratory,Universit´edeToulouseandUniversit´ePaulSabatier,CNRS,UMR5213,ToulouseF-31062,France(e-mail:vincent.bley@laplace.univ-tlse.fr;benoit.schlegel@laplace.univ-tlse.fr).
DigitalObjectIdentifier10.1109/TPEL.2010.2041557
subjecttothermomechanicalstresseswhentemperaturecyclingisinstalled.Thisleadstoawire-bondfatigueandeventuallyafailure[2].
Alternativeinterconnectiontechnologieshavebeendevel-opedtoovercomethelattershortcomingsinwire-bondingtech-nology,andthatallowa3-Dpackagingofpowermodulesinacompact-stackedlayerstructure[3]–[5].Theproposedtechnolo-giescanbedividedintofourcategories:solderinterconnection,interconnectionbysprings,pressurecontact,andinterconnec-tionbyelectroplatedmetallizations.Theadvancedinterconnec-tiontechnologiespermitadecreaseinthevaluesofparasiticinductanceandelectricalresistance.Theyalsoofferopportu-nitiestoimprovethethermalmanagementbyanaccesstothetopsideofthedice.However,the3-Dinterconnectiontechnolo-gieshavedrawbacks.Literaturereports,robustness,andrelia-bilitylimitsthesolderinterconnectiontechnologiesparticularlyunderrepetitivethermalcycling,andmoreoverunderhigherambienttemperature[6].Intheinterconnectionbysprings,theheat-fluxdissipationofthediceisrealizedmainlybytheback-sidebecausethespringshaveahighthermalresistance[4].Themanufacturingprocessofthespring-interconnectiontech-nologyiscomplexandlimitsitsacceptance.Concerningthepressurecontact,themainproblemsarethecomplicatedme-chanicalstructureandassemblyprograms.Moreover,someofthepressurecontacttechnologiesstillincludewirebondsforlow-powerconnection[7].Intheinterconnectionbyelectro-platedmetallizations,themajordrawbacksarethestressprob-lemsatthesolderlevelasthemechanicalrigidityoftheassem-blyisaugmented[7].Finally,fewalternativetechnologiestowirebondinghavebridgethegaptoindustrialprocessandmar-ketacceptance[8]–[9].Mostofthemremainlaboratory-scaleexperience.
Thisletterdetailstheexperienceofanalternativelaboratory-scaleinterconnectiontechnologycalledmicropostsintercon-nection.Ouraimistorealizea3-Dassembly,compatiblewithlow-costandhigh-volumemanufacturingsolutions;themicro-postsaregrowninonesteponawholesilicon-dicewafer,andboththetopandbottomofthediearebondedatthesametime.Furthermore,byprovidingathermalpathonbothsidesofthepowerdie(whereascoolingisdoneononesideonlywiththecurrenttechnology),this3-Dstructureissuitedtohigh-powerdevices.ThetechnologyissuesaredescribedinSectionII.SectionIIIshowstheelectricalcharacterizationofthemicrop-ostsinterconnectionandtheresultsarediscussedinSectionIV.ConclusionsandperspectivesaregiveninSectionV.
0885-8993/$26.00©2010IEEE
1668Fig.1.Schematicoftheproposeddieinterconnectionusingmicro-posts.
TABLEI
BONDINGMATERIALFAMILIESWITHTHEIRBONDINGANDREMELTING
TEMPERATURES[10]
II.MICROPOSTSINTERCONNECTIONOVERVIEW
Theproposedinterconnectionisbasedoncoppermicropoststhatareelectroplatedonthetopsideofthedie(seeFig.1).Themicropostshavetypicallyasquaresectionintherangeof100µm×100µm,upto300µm×300µm(tokeepasuffi-cientdensity)andaheightintherangeof100µm.Thedistancebetweentwomicropostsisfixedto300µminthefirststep.Sectiondimensionandpostinterdistancearevaluestobeopti-mized.Reducingsectionandincreasingpostdensityimpactfa-vorablythemechanicalrigidityandthethermalperformancesofarbutcoulddegradereliabilityperspectives.Copperpresentsagoodtradeoffbetweensufficientelectricalandthermalconduc-tivities,cost,availability,andmanufacturability.Themicropostsarerealizedbyelectroplating.Otherplatingmethodslikeevap-oration,sputtering,andelectrolessdonotallowinachievingaffordablythicknessescloseto100µmwithlargegrowthrate.Moreover,thisplatingmethodrequiresfewequipments,andisthuslowcost.
Thediewithitscoppermicropostsisattachedtothetopdirect-bondingcopper(DBC)substratebycopper(Cu)/tin(Sn)transientliquidphase(TLP)bondingstep(seeFig.1).TheTLPbondingstepusesalow-meltingtemperaturemetal(tin,in-dium,...)tobondtwohighmeltingtemperaturemetals(nickel,copper,silver,gold,...)together[10].DuringtheTLPbond-ingthatnecessitatesquiteahightemperature,pressure,andtime-sensitiveprocedure,thediffusionofthelow-meltingtem-peraturemetalinthehigh-meltingtemperaturemetalsinducesaformationofintermetalliccompounds.Thepresenceofin-termetalliccompoundspermitstohaveajointwitharemelt-ingtemperaturemoreimportantthanitsbondingtemperature.TableIlistssomeTLPbondingmaterialfamilieswiththeirbondingandremeltingtemperatures.TheDBCsubstratewasselectedforcompatibilitywiththecoppermicroposts.Othercombinationsmaybeconsideredbuthavenotbeentestedsofar.
IEEETRANSACTIONSONPOWERELECTRONICS,VOL.25,NO.7,JULY2010
Themaininterestsoftheproposedmicropostsinterconnec-tionaretheeliminationofasolderlayerbetweenthediepadsandtheinterconnectionontheonehand.Ontheotherhand,theCu/SnTLPbondingallowsinachievingjointswithahighremeltingtemperatureabove300◦C,andsoisasolutioncom-patiblesofarwithhightemperaturepackaging[10].Theotheradvantagesarethefollowing.Thesmallsizesofthemicropostspermittocreateamatrixofcontactsonausualpowerdie.Itdecreasesthevaluesofparasiticinductanceandelectricalresistance.Fromathermalpointofview,themicropostsinter-connectionoffersathermalaccessonthetopsideofthedie.Theproportionofheatfluxremovalthroughthistopconnexionhasnotbeenyetmeasuredbutfinite-elementmethodsimulationsindicatearatioof20%–30%ofthetotalheatflow(staticoper-atingconditionswithCOMSOL).Itisthensafetoconsiderapositiveimpactonthejunctionoperatingtemperatureofthedie.Thepossibilitytointroduceadielectricfluidand/orgelbetweenthemicropostswillallowimprovingtheheatfluxdissipationfromthetopsideofthedie.
III.MANUFACTURINGANDELECTRICALCHARACTERIZATION
OFTHEMICROPOSTSINTERCONNECTION
ThedifferentmanufacturingstepstorealizethemicropostsinterconnectiononachiparepresentedinFig.2.Beforetheelectroplatingofthemicroposts,thediepadsmustbecoveredwithathintitane(Ti)/copper(Cu)layer(20/100nm,respec-tively)ifthepadsarereadyforwirebondingorbump.Properlypreparedpadsforcopperelectroplatingwouldsuppressthispri-marypreparationofthedie.Titaneisusedasanadhesionlayerandcopperisemployedasaconductivelayerfortheelectro-platingstep.BeforethedepositionoftheTi/Culayer,apho-tolithographystepisolatesthediepads(photoresistthicknesscloseto2µm).ThisphotoresistwillpermittoremovetheTi/Culayeraroundthediepadsbylift-offaftertheelectroplatingofthemicroposts,andsotoavoidtheshortcircuitbetweenthediepads.
Asecondmaskingstepisperformedpriortotheelectrolyticgrowthofthemicropostsusingadryfilmphotoresist(RistonPM275dryfilmphotoresist[11])mainlyseenintheelectronicsindustrytorealizeprintedcircuitboards.Thedryfilmpho-toresistiscomposedofaphotoresistsandwichedbetweenapolyethyleneprotectivefoilandapolyestersupport.Itofferssomebenefitssuchasasimpleprocess,aremarkablerobust-nesstotheacidbath,adecreaseintheedgebeadsonthesub-strate,andalowcost.Thedryfilmphotoresisthasathicknessof75µmandanominalresolutionof50µm.TheprocesstorealizethepatterninonelayeroftheRistonPM275isthefol-lowing.Thedieisheatedat70◦Cfor1min.Thisheatingstepallowsimprovingthedryfilmphotoresistadhesiononthedie.Thepolyethylenefoilisremoved.Thephotoresistisdepositedbylaminationonthedie(100◦Cand0.3MPapressure).ItisthenexposedtoanUVsourcewithanintensitybetween12and15mW/cm2,andawavelengthof385nm,respectively.Theexposuretimeiscomprisedbetween5and7s,respectively.Afterlaminationandexposure,thepolyestersupportispeeledaway.Finally,thephotoresistisdevelopedwithaspraysystem
IEEETRANSACTIONSONPOWERELECTRONICS1669
Fig.2.Manufacturingprocessoftheproposedinterconnection.
inasodiumcarbonatesolutionat1%(5gofsodiumcarbonatedilutedin500mLofwater)during1minand30sandwithaprocessingtemperatureof30◦C.Theexperimentalelectrolyticcellhashorizontalelectrodes.Thisconfigurationallowsob-taininghomogeneousmicroposts.Theelectrolyticbathiscom-posedofpentahydratecoppersulphate(220g/L),sulphuricacid(32mL/L),hydrochloricacid(0.2mL/L),andbrightenerandleveleradditives(2mL/LofRubinT200-A,8mL/LofRubinT200-Gand2mL/LofRubinT200-E).Electroplatingofthemicropostsisperformedatambienttemperaturewithatypicalcurrentdensityof10mA/cm2.Theexperimentalgrowthrateofthemicropostsislinearandcloseto11µm/h,foracurrentdensityof10mA/cm2.Theminimaldeposittimehasbeensetto7h.ThisdeposittimeachievesamicropostsgrowthwithaheightlargerthanthethicknessoftheRistonPM275,andsoal-lowsthenforapolishingand/orgrindingstepofthemicropostsinordertoobtainaplanesurfaceandensureagoodelectri-calandthermalcontactbetweenthemicropostsandtheDBCsubstrate.Amechanicalpolishingisrealizedthankstoaclothpolishingdiskandadiamondliquidwithgrainsof9µmdownto1µminthelaboratory-scaleexperiment.Thinnergrainsareavailabletoimprovefurtherthestateofsurface.Fig.3showsthemicropostsforadeposittimeof8hbeforeandafterthepol-ishingstep.Theheightofthemicropostsis,respectively,96and62µmbeforeandafterthepolishingstep.Thisstepisessentialtoobtainafixedfinalthicknessofthedieincaseofmulti-dicemoduleswithdiceofdifferentinitialthickness.Aquitegoodtoleranceisachievablewithagrinding/polishingstep(namelyinthe100nmrangeandbetter).Thisavoidstheuseofinter-calarsthatmultiplytheinterfacesifnotincreasethenumberofsolderinterfaces[12].
AdiodediewithitspolishedmicropostsisattachedbyCu/SnTLPbondingtotheDBCsubstrate.Athintinlayer(thicknesslessthan1µm)isdepositedonthemicropostsandtheDBCsub-strate.ThetinthicknessandbondingtemperaturearededucedfromtheCu/SnphasediagraminordertoobtainaCu-rich/Sn
Fig.3.SEMimagesofthemicropostsforadeposittimeof8hbefore(a)andafter(b)thegrinding/polishingstep.
Fig.4.DiodeinterconnectedconcurrentlytotopandbottomDBC.
joint.Fig.4presentsa3.5kV-100AdiodewithmicropostsonanodesideandbondedconcurrentlytoatopandbottomDBCthroughCu/SnTLPproposal.Atinthicknessof0,5µm,apres-sureof10MPaandatemperatureof300◦Cduring7minhavebeenconsidered.ASEMimageoftheCu/SnjointbetweenamicropostsandaDBCisshowninFig.5.Asademonstrationofa3.5kV-100Adiodeintegrityafterinterconnectionprocess,thedirectelectricalcharacteristicispicturedinFig.6.Thischaracteristicisidenticaltothemanufacturerdatasheet[13].
IV.DISCUSSION
Theprevioussectionscoverthedetailsofafirstexperimentofaproposedinterconnectiontechniquetoavoidwirebondandsolder.Sofaronlythefeasibilityofthetechniquehasbeendemonstratedsincemanyissuesareunderinvestigation:influenceofmicropostdimensionswithregardtodiepaddi-mensionandpositioning,parametersofelectroplatinggrowth
1670Fig.5.
SEMimageofaCu/SnjointbetweenamicropostsandaDBC.
Fig.6.Directelectricalcharacteristicofa3.5kV-100Adiodewiththemi-cropostsinterconnection.
TABLEII
COMPARISONOFACTUALPACKAGINGTECHNOLOGIESWITHTHEMICROPOSTS
INTERCONNECTION
rate,toleranceofgrinding/polishingstep,optimalparametersofCu/SnTLPbonding,thermalperformancemeasurementofassembly,intrinsicreliabilityanalysis,interconnectionparasiticcomponentsmeasurementandreliabilityofamultidiceassem-bly.ProbablytheoptimalparametersofTLP-bondingdependontheindustrialsetup.However,thecopperintermetallicinter-faceisunderanalysistorelatetheshearforcecapabilitytothemetallurgicalcomposition.Thedimensionsofthemicropostshaveasignificantinfluenceonthethermalperformanceoftheassemblyandtheparasiticcomponents.Thelattercomponents
IEEETRANSACTIONSONPOWERELECTRONICS,VOL.25,NO.7,JULY2010
makesensewithrespecttocommutationwhatimpliestorealizeatwo-diceassembly(adiodeandaMOSFET,forexample).Theaccuracyofthegrinding/polishingstepisthenofprimaryim-portance.So,acompleteexperimentplanisrequiredandunderdevelopment.TableIIpresentsacomparisonofactualpackag-ingtechnologiestosituatethemicro-postsinterconnection.
V.CONCLUSION
Thisletterhaspresentedanalternativeinterconnectionsolu-tionforpowersemiconductordicethatwishestobecompati-blewith3-Dintegrationofpowermodules.Thedifferentsteps(electroplatingandassemblybyCu/SnTLPbonding)havebeendescribed.Afirstdemonstratorondiodediceprovesthefeasi-bilityoftheproposalastheelectricalcharacterizationshowsthatthediodehaskeptitsintegrityandasatisfyingelectricalconnectionisobtained.Nearfutureworkfocusestheproduc-tionofaswitching-cell(diode/MOSFET)forelectricaltran-sientcharacterizationsandthermomechanicalanalysis.More-over,electromagneticandthermalsimulationsofthemicropostsinterconnectionwillthenbevalidated.
REFERENCES
[1]K.Xing,F.-C.Lee,andD.Borojevic,“Extractionofparasiticswithinwire
bondIGBTmodules,”inProc.IEEEAppl.PowerElectron.Conf.Expo.,Feb.1998,pp.497–503.
[2]M.Ciappa,“Selectedfailuremechanismsofmodernpowermodules,”
Microelectron.Rel.,vol.42,no.4,pp.653–667,Apr.2002.
[3]J.-N.Catala,J.-G.Bai,X.Liu,S.Wen,andG.-Q.Lu,“Threedimensional
packagingforpowersemiconductordevicesandmodules,”IEEETrans.Adv.Packag.,vol.28,no.3,pp.404–412,Aug.2005.
[4]X.He,X.Zeng,X.Yang,andZ.Wang,“Ahybridintegratedpower
electronicmodulebasedonpressurecontacttechnology,”inProc.IEEEPowerElectron.Spec.Conf.,Jun.2006,pp.1–5.[5]E.Vagnon,J.-C.Cr´ebier,Y.Avenas,andP.-O.Jeannin,“Studyandrealiza-tionofalowforce3Dpress-packpowermodule,”IEEEPowerElectron.
Spec.Conf.,Jul.2008,pp.1048–1053.
[6]J.-G.Bai,J.-N.Catala,andG.-Q.Lu,“Comparativethermalandther-momechanicalanalysesofsolderbumpanddirectsolderbondedpowerdevicepackageshavingdoublesidedcoolingcapability,”inProc.IEEEAppl.PowerElectron.Conf.Expo.,Feb.2004,vol.1,pp.1240–1246.[7]L.-H.Zhang,X.Yang,F.Wang,andZ.-A.Wang,“Pressurecontactpack-agingforhybridelectricvehicledrive,”inProc.IEEEPowerElectron.Spec.Conf.,Jun.2007,pp.2228–2233.
[8]M.Mermet-Guyennet,“Newstructureofpowerintegratedmodule,”in
Proc.Int.Conf.Integr.PowerSyst.,Jun.2006,pp.133–138.
[9]U.ScheuermannandF.Ebersberger,“Packagingoflargeareapower
chips—Extendingthelimitsofstandardmoduletechnology,”[Online].Available:http://www.semikron.com
[10]W.Welch,J.Chae,andK.Najafi,“TransferofmetalMEMSpackages
usingawafer-levelsoldertransfertechnique,”IEEETrans.Adv.Packag.,vol.28,no.4,pp.643–649,Nov.2005.
[11]Dupont.(2006).“DatasheetDupontPlatemasterPM200,”[Online].Avail-able:http://www2.dupont.com.
[12]Z.Liang,J.-D.V.Wyk,F.-C.Lee,D.Borojevic,E.-P.Scott,Z.Chen,and
Y.Pang,“Integratedpackagingofa1kWswitchingmoduleusinganovelplanarintegrationtechnology,”IEEETrans.PowerElectron.,vol.19,no.1,pp.242–250,Jan.2004.
[13]“DatasheetofSIDC185D350A6diode,”Infineon,[Online].Available:
http://www.infineon.com.
[14]R.Fillion,E.Delgado,P.McConnelee,andR.Beaupre,“Ahighper-formancepolymerthinfilmpowerelectronicspackagingtechnology,”inProc.Adv.Microelectron.,Sep.2003,pp.7–13.
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